• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.2
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• pp.85-91
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• 1998

This paper describes an study electric injection system for diesel engines. It is needed effective fuel injection which controls the solenoid valve of fuel pump. To solve this, this paper proposes DCC-PWM method which can realize fast reply and low holding current for solenoid valve on/off. For the proposed design method, simulation tools of ACSL are used to analyze the system. And the single-chip microcomputer is used to reduce the size of controller and to improve flexibility. And the systems validity can be verified through the experimental results.

• ETRI Journal
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• v.38 no.3
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• pp.479-486
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• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.2
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• pp.75-82
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• 2000

In this paper, described is the comparison of performances based on the computer simulation under IMT-2000 environment between multicode and multicarrier CDMA system for the design of wireless systems using wideband CDMA technology. From simulation results, it can be concluded that both multicode and multicarrier CDMA scheme show comparable performances. Diversity scheme of RAKE receiver is indispensible for both multicode and multicarrier CDMA systems under IMT-2000 outdoor B and vehicular B channel environment. Either Hadamard matrix or PN sequence can be used as the orthogonal code as far as the orthogonality is kept. Finally, with increasing chip rate and less users, performance is getting better.

• Journal of the Korea Society of Computer and Information
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• v.13 no.6
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• pp.195-201
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• 2008

We proposed that is suitable network environment and wire/wireless communication network, easy of implementation, security level preservation, scalable & reconfigurable to TCP/IP protocol architecture to implement suitable smart card MS-Serpent cryptographic algorithm for smart card by hardware base chip level that software base is not implement. Implemented MT-Serpent cryptosystem have 4,032 in gate counter and 406.2Mbps@2.44MHz in throughput. Implemented MS-Serpent cryptographic algorithm strengthens security vulnerability of TCP/IP protocol to do to rescue characteristic of smart card and though several kind of services are available and keep security about many user in wire/wireless environment, there is important purpose.

• 전자공학회논문지 IE
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• v.46 no.2
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• pp.7-10
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• 2009

This paper presents the implementation of libraries of hardware modules for genetic algorithm using VHDL. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results and analysis for several fitness functions. It can be seen that our design works well for the three examples.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1506-1511
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• 2004

The error control of digital transmission system is a very important subject because of the noise effects, which is very sensitive to transmission performance of the digital communication system It employs a modified Euclid's algorithm to compute the error-location polynomial and error-magnitude polynomial of input data. The circuit size is reduced by selecting the Modified Euclid's Algorithm with one Euclid Cell of mutual operation. And the operation speed of Decoder is improved by using ROM and parallel structure. The proposed Encoder and Decoder are simulated with ModelSim and Active-HDL and synthesized with Synopsys. We can see that this chip is implemented on Xilinx Virtex2 XC2V3000. A share of slice is 28%. nut speed of this paper is 45Mhz.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.1089-1094
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• 2000

소형 고성능 가전기기를 실현하기 위한 다기능 고집적의 실리콘화에 대응하기 위하여 반도체 업계는 SoC(System On a Chip) 설계, 반도체 지적 재산권인 IP(Intellectual Property)에 관한 연구를 두개의 핵심 연구 항목으로 설정하여 진행되어 왔다. 반도체 레이아웃 이식 자동화 시스템은 설계 재활용(Design Reuse), IP의 실용화와 확산을 위한 핵심 연구 과제 중의 하나로써, Time-To-Market 과 Time-To-Money 를 동시에 가능토록 하는 근간의 기술이 된다. 본 연구는 정확하고 고속의 IP내의 반도체 소자 인식 알고리즘, 그래프를 이용한 제한 조건의 구현과 해석, 향상된 컴팩션(Compaction) 알고리즘의 연구로 말미암아 기존의 연구 결과 대비 평균 20배의 속도 향상과 평균 41%의 메모리만을 사용함으로써 경쟁 기술 대비 월등한 우위를 보이고 있다. 이로써, 대형의 반도체 설계 도면의 처리를 가능하도록 하였으며, 반도체 IP의 응용성(flexibility)을 부여 함으로써, IP의 재활용의 기초 연구와 SoC 설계 확산에 지렛대 역할을 하는 연구가 되리라고 예측한다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.664-670
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• 2018

In modern society, CCTV, which is the eye of surveillance, is being used to collect image data in various ways in daily life. CCTV is used not only for security, surveillance, and crime prevention but also in many fields such as automobile and black box. In this paper, we have developed a STM32F407 ARM chip based camera system for various applications. In order to develop camera system, modeling of camera system based on 3D structure was carried out in SolidWorks environment. The PCB board design was developed to extract the PCB parts from the camera system modeling files into iges files, convert them from the Altium Designer tool into 3D and 2D boards, After designing the camera system circuit and PCB, we have been studying the implementation of the stable system by using TRM (Thermal Risk Management) tool to cope with the heat simulation generated on the board.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.43-51
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• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.