• Title/Summary/Keyword: synthesis algorithm

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A Frequency Transfer Function Synthesis of QFT Using Total Least Squares Method (완전최소자승법을 이용한 QFT의 주파수 전달함수 합성법)

  • Kim, Ju-Sik;Lee, Sang-Hyuk
    • Journal of Institute of Control, Robotics and Systems
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    • v.8 no.8
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    • pp.649-654
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    • 2002
  • The essential philosophy of the QFT(Quantitative Feedback Theory) is that a suitable controller can be found by loop shaping a nominal loop transfer function such that the frequency response of this function does not violate the QFT bounds. The loop shaping synthesis involves the identification of a structure and its specialization by means of the parameter optimization. This paper presents an optimization algorithm to estimate the controller parameters from the frequency transfer function synthesis using the TLS(Total Least Squares) in the QFT loop shaping procedure. The proposed method identifies the parameter vector of the robust controller from an overdetermined linear system developed from rearranging the two dimensional system matrices and output vectors obtained from the QFT bounds. The feasibility of the suggested algorithm is illustrated with an example.

Control System Synthesis Using BMI: Control Synthesis Applications

  • Chung, Tae-Jin;Oh, Hak-Joon;Chung, Chan-Soo
    • International Journal of Control, Automation, and Systems
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    • v.1 no.2
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    • pp.184-193
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    • 2003
  • Biaffine Matrix Inequality (BMI) is known to provide the most general framework in control synthesis, but problems involving BMI's are very difficult to solve because nonconvex optimization should be solved. In the previous paper, we proposed a new solver for problems involving BMI's using Evolutionary Algorithms (EA). In this paper, we solve several control synthesis examples such as Reduced-order control, Simultaneous stabilization, Multi-objective control, $H_{\infty}$ optimal control, Maxed $H_2$ / $H_{\infty}$control design, and Robust $H_{\infty}$ control. Each of these problems is formulated as the standard BMI form, and solved by the proposed algorithm. The performance in each case is compared with those of conventional methods.

Pattern Synthesis of Rotated-type Conformal Array Antenna Using Enhanced Adaptive Genetic Algorithm (향상된 적응형 유전 알고리즘을 이용한 회전체형 컨포멀 배열 안테나의 패턴 합성)

  • Seong, Cheol-Min;Kwon, Oh-Hyeok;Park, Dong-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.8
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    • pp.758-764
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    • 2015
  • This paper describes the pattern synthesis of array antenna which conforms to a metallic curved surface formed by the rotation of a quadratic function by using EAGA(Enhanced Adaptive Genetic Algorithm). Three rotated-type conformal surfaces are realized by changing the coefficient of the quadratic function and the pattern of each conformal array antenna is synthesized. In order to reduce the overall time of pattern synthesis, the transformed active element pattern obtained by the active element pattern of the 2-dimensional planar array using Euler angles rotation is utilized instead of the active element pattern of the 3-dimensional conformal array antenna itself. To verify validity of the proposed synthesis procedure, the synthesized patterns using EAGA are compared with those obtained by MWS.

Stepwise Refinement Data Path Synthesis Algorithm for Improved Testability (개선된 테스트 용이화를 위한 점진적 개선 방식의 데이타 경로 합성 알고리즘)

  • Kim, Tae-Hwan;Chung, Ki-Seok
    • Journal of KIISE:Computer Systems and Theory
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    • v.29 no.6
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    • pp.361-368
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    • 2002
  • This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tacks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.

Optimal Synthesis Method for Binary Neural Network using NETLA (NETLA를 이용한 이진 신경회로망의 최적 합성방법)

  • Sung, Sang-Kyu;Kim, Tae-Woo;Park, Doo-Hwan;Jo, Hyun-Woo;Ha, Hong-Gon;Lee, Joon-Tark
    • Proceedings of the KIEE Conference
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    • 2001.07d
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    • pp.2726-2728
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    • 2001
  • This paper describes an optimal synthesis method of binary neural network(BNN) for an approximation problem of a circular region using a newly proposed learning algorithm[7] Our object is to minimize the number of connections and neurons in hidden layer by using a Newly Expanded and Truncated Learning Algorithm(NETLA) for the multilayer BNN. The synthesis method in the NETLA is based on the extension principle of Expanded and Truncated Learning(ETL) and is based on Expanded Sum of Product (ESP) as one of the boolean expression techniques. And it has an ability to optimize the given BNN in the binary space without any iterative training as the conventional Error Back Propagation(EBP) algorithm[6] If all the true and false patterns are only given, the connection weights and the threshold values can be immediately determined by an optimal synthesis method of the NETLA without any tedious learning. Futhermore, the number of the required neurons in hidden layer can be reduced and the fast learning of BNN can be realized. The superiority of this NETLA to other algorithms was proved by the approximation problem of one circular region.

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A genetic-algorithm-based high-level synthesis for partitioned bus architecture (유전자 알고리즘을 이용한 분할 버스 아키텍처의 상위 수준 합성)

  • 김용주;최기영
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.3
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    • pp.1-10
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    • 1997
  • We present an approach to high-level synthesis for a specific target architecture-partitioned bus architecture. In this approach, we have specific goals of minimizing data transfer length and number of buses in addition to common synthesis goals such as minimizing number of control steps and satisfying given resource constraint. Minimizing data transfer length and number of buses can be very important design goals in the era of deep submicron technology in which interconnection delay and area dominate total delay and area of the chip to be designed. in partitioned bus architecture, to get optimal solution satisfying all the goals, partitioning of operation nodes among segments and ordering of segments as well as scheduling and allocation/binding must be considered concurrently. Those additional goals may impose much more complexity on the existing high-level synthesis problem. To cope with this increased complexity and get reasonable results, we have employed two ideas in ur synthesis approach-extension of the target architecture to alleviate bus requirement for data transfer and adoption of genetic algorithm as a principal methodology for design space exploration. Experimental results show that our approach is a promising high-level synthesis mehtodology for partitioned bus architecture.

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A SoC Design Synthesis System for High Performance Vehicles (고성능 차량용 SoC 설계 합성 시스템)

  • Chang, Jeong-Uk;Lin, Chi-Ho
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.3
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    • pp.181-187
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    • 2020
  • In this paper, we proposed a register allocation algorithm and resource allocation algorithm in the high level synthesis process for the SoC design synthesis system of high performance vehicles We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the resources allocation algorithm. The algorithm assigns the functional operators so that the number of connecting signal lines which are repeatedly used between the operators would be minimum. This algorithm provides regional graphs with priority depending on connected structure when the registers are allocated. The registers with connecting structure are allocated to the maximum cluster which is generated by the minimum cluster partition algorithm. Also, it minimize the connecting structure by removing the duplicate inputs for the multiplexor in connecting structure and arranging the inputs for the multiplexor which is connected to the operators. In order to evaluate the scheduling performance of the described algorithm, we demonstrate the utility of the proposed algorithm by executing scheduling on the fifth digital wave filter, a standard bench mark model.

Synthesis of Automatically Path-Generating Four-Bar Linkage Using NURBS (NURBS를 이용한 4절 링크의 자동 경로 생성)

  • Hwang, Deuk-Hyun;Yang, Hyun-Ik
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.18 no.6
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    • pp.576-584
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    • 2009
  • Up to now, it has been said that no satisfactory computer solution has been found for synthesizing four-bar linkage based on the prescribed coupler link curve. In our study, an algorithm has been developed to improve the design synthesis of four bar linkage based on the 5 precision points method. The suggested algorithm generates the desired coupler curve by using NURBS, and then the generated curve approximates as closely as possible to the desired curve representing coupler link trajectory. Also, when comparing each generated curve by constructing the control polygon, rapid comparison is easily achieved by applying convex hull of the control polygon. Finally, an optimization process using ADS is incorporated into the algorithm based on the 5 precision point method to reduce the total optimization process time. As for examples, two four bar linkages were tested and the result well demonstrated the effectiveness of the algorithm.

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Study on Pattern Synthesis of Conformal Phased Array Antenna (컨포멀 위상 배열 안테나의 패턴 합성에 대한 고찰)

  • Park, Dong-Chul;Kwon, Oh-Hyuk;Ryu, Hong-Kyun;Lee, Kyu-Song
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.12
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    • pp.1031-1043
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    • 2015
  • This paper describes the pattern synthesis method of two kinds of conformal array antenna using the Enhanced Adaptive Genetic Algorithm (EAGA). One is the $1{\times}16$ conformal array antenna on a curved cylindrical metallic surface with quadratic function, and the other is the 18-element conformal arrary antenna on a metallic surface obtained by the rotation of a quadratic function curve around the axis. The active element pattern is utilized in the pattern synthesis. Especially for the case of the rotated-type conformal array antenna the transformed active element pattern obtained from the Euler's angle rotation of the active element pattern of the planar concentric array is utilized, which reduces the synthesis time a lot. To verify the validity of the proposed synthesis method the MATLAB results are compared with the MWS results. Furthermore, for the case of $1{\times}16$ conformal array antenna the measured results are compared with the MATLAB synthesized results.

Analysis of Error Tolerance in Sonar Array by the Genetic Algorithm (유전자 알고리즘에 의한 소나 배열 소자의 허용오차 분석)

  • 양수화;김형동
    • The Journal of the Acoustical Society of Korea
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    • v.22 no.6
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    • pp.496-504
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    • 2003
  • In this paper, the error tolerance of each array element to ensure a given specified error level for the array pattern is analyzed using the Genetic Algorithm. In the conventional deterministic method for synthesis of sonar way problems the computational resource required in the simulation grows rapidly as the number of way elements increases. To alleviate this numerical inefficiency, the Monte-Carlo method may be considered as an alternative technique for array syntheses. However, it is difficult to apply the method to the synthesis of array patterns because of its relatively lower accuracy in spite of moderate computational complexity. A new analysis method for estimating error tolerances in sonar arrays is Proposed since the Genetic Algorithm has significant promise to efficiently solve way synthesis problems. Through several numerical tests in linear and planar arrays, it is demonstrated that the proposed method can provide accurate results for error tolerances of sonar arrays.