• 한국전기전자재료학회논문지
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• 제26권3호
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• pp.246-251
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• 2013

Screen printing is commonly used to form the front/back electrodes in silicon solar cell. But it has caused high resistance and low aspect ratio, resulting in decreased conversion efficiency in solar cell. Recently the plating method has been combined with screen-printed c-Si solar cell to reduce the resistance and improve the aspect ratio. In this paper, we investigated the effect of light induced silver plating with screen-printed c-Si solar cells and compared their electrical properties. All wafers were textured, doped, and coated with anti-reflection layer. The metallization process was carried out with screen-printing, followed by co-fired. Then we performed light induced Ag plating by changing the plating time in the range of 20 sec~5min with/without external light. For comparison, we measured the light I-V characteristics and electrode width by optical microscope. During plating, silver ions fill the porous structure established in rapid silver particle sintering during co-firing step, which results in resistance decrease and efficiency improvement. The plating rate was increased in presence of light lamp, resulting in widening the electrode with and reducing the short-circuit current by shadowing loss. With the optimized plating condition, the conversion efficiency of solar cells was increased by 0.4% due to decreased series resistance. Finally we obtained the short-circuit current of 8.66 A, open-circuit voltage of 0.632 V, fill factor of 78.2%, and efficiency of 17.8% on a silicon solar cell.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1079-1081
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• 2007

An L-band Linear Accelerator System for E-beam sterilization is under construction for bio-technology application. The klystron-modulator system as an RF microwave source has an important role as major components to offer the system reliability for long time steady-state operations. A PFN line type pulse generator with a peak power of 71.5-MW, $7\;{\mu}s$, 285 pps is required to drive a high-power klystron. The high power pulse transformer has a function of transferring pulse energy from a pulsed power source to a high power load. The pulse transformer producing a pulse with a peak voltage of 275 kV is required to produce 30-MW peak and 60 kW average RF output power at the frequency of 1.3-GHz. We have designed the high power pulse transformer with 1:13 step-up ratio. The peak and average power capability is 71.5-MW (275 kV, 260 A at load side with $7\;{\mu}s$ pulse width) and 130 kW, respectively. In this paper, we present measurements and its analysis on the design parameters, and an initial test result as well as a design concept on the high-power pulse transformer.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.93-94
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• 2007

An essential step for SERGI is to show the TRANSFORMER PROTECTOR (TP) efficacy for all transformers and all types of rupture of insulation. Its research program philosophy is thus to maintain a strong connection between experiments and the theoretical developments. Up to now, two TP test campaigns have been performed, both under the worst conditions by creating low impedance faults leading to electrical arcs inside the transformer tank dielectric oil. In 2002, Electricite de France performed 28 TP tests. Then, in 2004, a second campaign of 34 TP tests was carried out by CEPEL, the Brazilian independent High Voltage Laboratory. For the 62 tests, each transformer was equipped with the TP, which reacts directly to the moving dynamic pressure peak, shock wave, caused by the low impedance fault. When an electrical arc occurs, only one pressure peak is generated. The initial energy transfer is almost instantaneous, and so is the phase change. Because of the oil inertia, the gas is very quickly pressurised. As it is more difficult to vaporise a liquid than to crack oil-vapour into smaller molecules, the arc location would mainly remain in the gaseous phase after and less gas will be produced. As a result, when comparing tests for which pressure peaks are respectively equal to 8 bar (116 psi) and 8.8 bar (127 psi), the corresponding arc energies vary by an order 10 of magnitude (0.1 MJ and 1 MJ respectively). The correlation of the results obtained between arc energy and dynamic pressure demonstrates that the arc energy is not the key parameter during transformer tank explosion, which is in opposition with the common electrical engineers belief.

• 한국진공학회지
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• 제7권2호
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• pp.88-93
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• 1998

본 연구에서는 기계-화학적 연마(Chemical-Mechanical-Polishing: CMP)공정을 이용 하여 게이트 전극을 가지는 실리콘 전계방출 소자를 제작하였으며, 또한 그 전자방출 특성 을 분석하였다. 실리콘 전계방출 소자를 제작하기 위해 실리콘을 두단계로 이루어진 건식식 각과 산화공정으로 팁을 뾰족하게 만들었으며, 게이트를 형성하기 위하여 고 선택비를 가지 는 CMP공정을 사용하였으며, 연마 시간과 연마 압력의 변화로 게이트 높이와 개구의 직경 을 쉽게 조절할 수 있었다. 또한, CMP공정시 발생되는 디싱(dishing)문제를 산화막 마스킹 을 사용함으로 해결하여 자동 정렬된 게이트전극의 개구를 깨끗하게 형성할 수 있었다. 제 작된 에미터의 높이와 팁끝의 반경은 각각 1.1$\mu$m, 100$\AA$정도이며, 제작된 2809개의 팁 어 레이로 80V의 게이트전압에서 31$\mu$A의 방출전류를 얻을 수 있었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.754-758
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• 2005

Optimization of process variables such as arc current, welding voltage and welding speed in terms of the weld characteristics desired is the key step in achieving high quality and improving performance characteristics without increasing the cost. Consequently, incorrect settings of those process variables give rise to deviations in the welding characteristics from the desired bead geometry. Therefore, trainee welders are referred to the tabulated information relating different metal types and thickness as to recommend the desired values of process variables. Basically, the bead geometry plays an important role in determining the mechanical properties of the weld. So that it is very important to select the process variables for obtaining optimal bead geometry. However, it is difficult for the traditional identification methods to provide an accurate model because the optimized welding process is non-linear and time-dependent. In this paper, the possibilities of the Infra-red sensor in sensing and control of the bead geometry in the automated welding process are presented. Infra-red sensor is a well-known method to deal with the problems with a high degree of fuzziness so that the sensor is employed to build the relationship between process variables and the quality characteristic the proposed above respectively. Based on several neural networks, the mathematical models are derived from extensive experiments with different welding parameters and complex geometrical features. The developed system enables to select the optimal welding parameters and control the desired weld dimensions during arc welding process.

• 한국전기전자재료학회논문지
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• 제32권5호
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• pp.376-381
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• 2019

In this work, we evaluated the structural, electrical and optical properties of $Ge_8Sb_2Te_{11}$ and Cu-doped $Ge_8Sb_2Te_{11}$ thin films prepared by rf-magnetron reactive sputtering. The 200-nm-thick deposited films were annealed in a range of $100{\sim}400^{\circ}C$ using a furnace in an $N_2$ atmosphere. The amorphous-to-crystalline phase changes of the thin films were investigated by X-ray diffraction (XRD), UV-Vis-IR spectrophotometry, a 4-point probe, and a source meter. A one-step phase transformation from amorphous to face-centered-cubic (fcc) and an increase of the crystallization temperature ($T_c$) was observed in the Cu-doped film, which indicates an enhanced thermal stability in the amorphous state. The difference in the optical energy band gap ($E_{op}$) between the amorphous and crystalline phases was relatively large, approximately 0.38~0.41 eV, which is beneficial for reducing the noise in the memory devices. The sheet resistance($R_s$) of the amorphous phase in the Cu-doped film was about 1.5 orders larger than that in undoped film. A large $R_s$ in the amorphous phase will reduce the programming current in the memory device. An increase of threshold voltage ($V_{th}$) was seen in the Cu-doped film, which implied a high thermal efficiency. This suggests that the Cu-doped $Ge_8Sb_2Te_{11}$ thin film is a good candidate for PRAM.

• 전자공학회논문지
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• 제53권3호
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• pp.46-55
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• 2016

본 논문에서는 IF 대역의 고속 신호처리 시스템 응용을 위해 높은 동적성능을 가지는 13비트 100MS/s ADC를 제안한다. 제안하는 ADC는 45nm CMOS 공정에서 동작 사양을 최적화하기 위해 4단 파이프라인 구조를 기반으로 하며, 광대역 고속 샘플링 입력단을 가진 SHA 회로는 샘플링 주파수를 상회하는 높은 주파수의 입력신호를 적절히 처리한다. 입력단 SHA 및 MDAC 증폭기는 요구되는 DC 이득 및 넓은 신호범위를 얻기 위해 이득-부스팅 회로 기반의 2단 증폭기 구조를 가지며, 바이어스 회로 및 증폭기에 사용되는 소자는 부정합을 최소화하기 위해 동일한 크기의 단위 소자를 반복적으로 사용하여 설계하였다. 한편, 온-칩 기준전류 및 전압회로에는 배치설계 상에서 별도의 아날로그 전원전압을 사용하여 고속 동작 시 인접 회로 블록에서 발생하는 잡음 및 간섭에 의한 성능저하를 줄였다. 또한, 미세공정상의 잠재적인 불완전성에 의한 성능저하를 완화하기 위해 다양한 아날로그 배치설계 기법을 적용하였으며, 전체 ADC 칩은 $0.70mm^2$의 면적을 차지한다. 시제품 ADC는 45nm CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 각각 최대 0.77LSB, 1.57LSB의 값을 가지며, 동적성능은 100MS/s 동작 속도에서 각각 최대 64.2dB의 SNDR과 78.4dB의 SFDR을 보여준다. 본 시제품 ADC는 $2.0V_{PP}$의 넓은 입력신호범위를 처리하는 동시에 IF 대역에서 높은 동적성능을 확보하기 위해 사용공정상의 최소 채널 길이가 아닌 긴 채널 기반의 소자를 사용하며, 2.5V의 아날로그 전압, 2.5V 및 1.1V 두 종류의 디지털 전원전압을 사용하는 조건에서 총 425.0mW의 전력을 소모한다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.189-189
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• 2012

Lead sulfide (PbS) nanocrystal quantum dots (NQDs) are promising materials for various optoelectronic devices, especially solar cells, because of their tunability of the optical band-gap controlled by adjusting the diameter of NQDs. PbS is a IV-VI semiconductor enabling infrared-absorption and it can be synthesized using solution process methods. A wide choice of the diameter of PbS NQDs is also a benefit to achieve the quantum confinement regime due to its large Bohr exciton radius (20 nm). To exploit these desirable properties, many research groups have intensively studied to apply for the photovoltaic devices. There are several essential requirements to fabricate the efficient NQDs-based solar cell. First of all, highly confined PbS QDs should be synthesized resulting in a narrow peak with a small full width-half maximum value at the first exciton transition observed in UV-Vis absorbance and photoluminescence spectra. In other words, the size-uniformity of NQDs ought to secure under 5%. Second, PbS NQDs should be assembled carefully in order to enhance the electronic coupling between adjacent NQDs by controlling the inter-QDs distance. Finally, appropriate structure for the photovoltaic device is the key issue to extract the photo-generated carriers from light-absorbing layer in solar cell. In this step, workfunction and Fermi energy difference could be precisely considered for Schottky and hetero junction device, respectively. In this presentation, we introduce the strategy to obtain high performance solar cell fabricated using PbS NQDs below the size of the Bohr radius. The PbS NQDs with various diameters were synthesized using methods established by Hines with a few modifications. PbS NQDs solids were assembled using layer-by-layer spin-coating method. Subsequent ligand-exchange was carried out using 1,2-ethanedithiol (EDT) to reduce inter-NQDs distance. Finally, Schottky junction solar cells were fabricated on ITO-coated glass and 150 nm-thick Al was deposited on the top of PbS NQDs solids as a top electrode using thermal evaporation technique. To evaluate the solar cell performance, current-voltage (I-V) measurement were performed under AM 1.5G solar spectrum at 1 sun intensity. As a result, we could achieve the power conversion efficiency of 3.33% at Schottky junction solar cell. This result indicates that high performance solar cell is successfully fabricated by optimizing the all steps as mentioned above in this work.

• 대한전자공학회논문지SD
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• 제42권12호
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• pp.53-60
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• 2005

본 논문에서는 저 전력 멀티미디어 응용을 위한 10b 100 MS/s $1.4\;mm^2$ CMOS A/D 변환기(ADC)를 제안한다. 제안하는 ADC는 해상도 및 속도 사양을 만족시키면서, 면적 및 전력 소모를 최소화하기 위해 기존의 다단 구조가 아닌 2단 파이프라인 구조를 사용하였다. 그리고 10 비트 해상도에서 1.2 Vp-p의 단일 및 차동 입력 신호 처리 대역폭을 넓히기 위해 입력 샘플-앤-홀드 증폭기에는 게이트-부트스트래핑 회로를 적용하며, 6 비트 해상도를 필요로 하는 두 번째 단의 flash ADC에는 오픈-루프 오프셋 샘플링 기법을 적용하였다. 또한 커패시터 등 소자 부정합에 의해 해상도에 크게 영향을 줄 수 있는 MDAC의 커패시터에는 3차원 완전 대칭 구조를 갖는 레이아웃 기법을 제안하였다. 기준 전류/전압 발생기는 온-칩으로 집적하여 잡음 에너지를 줄였으며, 필요시 선택적으로 다른 크기의 기준 전압을 외부에서 인가하도록 설계하였다. 제안하는 10b 시제품 ADC는 0.18 um CMOS 공정으로 제작되었고, 측정된 DNL 및 INL은 각각 0.59 LSB, 0.77 LSB 수준을 보여준다. 또한 100 MS/s의 샘플링 속도에서 SNDR 및 SFDR이 각각 54 dB, 62 dB 수준을 보였으며, 전력 소모는 56 mW이다.

• 대한전자공학회논문지SD
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• 제41권1호
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• pp.53-60
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• 2004

본 논문에서는 샘플링 주파수보다 더 높은 입력 대역폭을 얻기 위해서 개선된 부트스트래핑 기법을 적용한 l0b 150 MSample/s A/D를 제안한다. 제안하는 ADC는 다단 파이프라인 구조를 사용하였고, MDAC의 캐패시터 수를 $50\%$로 줄이는 병합 캐패시터 스위칭 기법을 적용하였으며, 저항 및 캐패시턴스의 부하를 고속에서 구동할 수 있는 기준 전류/전압 발생기와 고속 측정이 용이한 decimator를 온-칩으로 구현하였다. 제안하는 ADC 시제품은 0.18 um IP6M CMOS 공정을 이용하여 설계 및 제작되었고, 시제품 ADC의 측정된 DNL과 INL은 각각 $-0.56{\~}+0.69$ LSB, $-1.50{\~}+0.68$ LSB 수준을 보여준다. 또한, 시제품 측정결과 150 MSample/s 샘플링 주파수에서 52 dB의 SNDR을 얻을 수 있었고, 입/출력단의 패드를 제외한 시제품 칩 면적은 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm)이며, 최대 동작 주파수인 150 MHz에서 측정된 전력 소모는 123 mW이다.