• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.12
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• pp.751-758
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• 2004

This paper presents a new method to compensate the non-linearity for matrix converter drives using PQR instantaneous Power theory. The non-linearity of matrix converter drives such as commutation delay, turn-on and turn-off time of switching device, and on-state switching device voltage drop is modelled by PQR power theory and compensated using a reference current control scheme. The proposed method does not need any additional hardware and off-line experimental measurements. The proposed compensation method is applied for high performance induction motor drives using a 3 kW matrix converter system without a speed sensor. Simulation and experimental results show the proposed method using PQR power theory Provides good compensating characteristic.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.268-271
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• 2001

This paper presents observer-based on-line overload monitoring scheme for a PMSM(Permanent Magnet Synchronous Motor) drive system. Proposed scheme is to monitor overload status of motor drive system at remote place. The drive system is previously installed on main system and has no communication function. Proposed scheme consists of intelligent sensing head and monitoring part. Intelligent sensing head acquire motor 3-Phase currents and transmit data to monitoring part over serial communication interface. Monitoring part estimates motor speed using state observer. By comparing estimated speed with reference speed, we can detect motor fault. In this scheme observed information must coded and transmitted over a digital communication channel with finite capacity. We consider communication constraint as time delay and we design discrete-time observer. The proposed scheme is tested on the actual drive system.

• Proceedings of the KIEE Conference
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• 1999.07b
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• pp.633-635
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• 1999

We design to the temperature control system based on Receding horizon control(RHC) with a terminal output weighting for stochastic state model. This system has a large time delay, a nonlinear temperature characteristics, a perturbation, a disturbance, etc. In this paper, we show that RHC can easily be applied to the system to track the desired temperature, since it takes the receding horizon strategy for both controller and filter.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2161-2163
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• 2004

This paper focuses on congestion control for ATM network with uncertain time-variant delays. The time-variant delays can be distinguished into two distinct components. The first one that is represented by time-variant queueing delays in the intermediate switches is occurred in the return paths of RM cells. The next one is a forward path delay. It is solved by the VBR Model which quantifies the data propagation from the sources to the switch. Robust $H_{\infty}$ control is studied for solving congestion problem with norm-bounded time-varying uncertain parameters. The suitable robust $H_{\infty}$ controller is obtained from the solution of a convex optimization problem including terms of LMIs.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.267-268
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• 2008

TD-SCDMA is considered as an innovative Chinese 3G technology adopted by the ITU for the IMT-2000 family. TD-SCDMA combines TDMA and CDMA components to provide more efficient use of radio resources. According to the traffic volume and activity level, the operation mode of a mobile terminal can change from one state to other states. This paper focuses on the problem of recovery delay from inactive states, and proposes a resource management algorithm, which holds some resources for rapid recovery of service after the service determines to release the dedicated resources.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.57.1-57
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• 2001

The objectives of congestion control in ATM (Asynchronous Transfer Mode) networks are maximum utilization of network resources, acceptable level of low cell loss and fairness among all VCs (Virtual Connections). In this paper, we present a congestion control algorithm which is based on state space model, The proposed controller uses optimal control algorithms (LQR, Mixed-LQR), where control parameters can be designed to ensure the stability of the control loop in a control theoretic sense, over the propagation delay. We show how the control mechanism can be used to design a controller to support ABR service based on feedback of explicit rates. Simulation results are presented to substantiate our claim.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.148.2-148
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• 2001

The most important difference of an airship from conventional vehicle is that it has the apparent mass and inertia provided from the existence of Helium gas inside the airship. To acquire To acquire the exact response of the airship, the longitudinal responses of airship with respect to the vertical gust, which is the non-linear system, have been studied. An Airship has neutral buoyancy in equilibrium state. When it moves, its motion shows much difference comparing with conventional aircraft. Here, we compare two cases, the one has the apparent mass and the other hasn´t. With the apparent mass, the magnitude of the former response is smaller than the latter, while the frequency is higher. However, the apparent mass delay ...

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.102.2-102
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• 2001

In this study, a solid-state laser system adopting a new real time multi-discharge (RTMD) method in which three flashlamps are turned on consecutively was designed and fabricated to examine the pulse width and the pulse shape of the laser beams depending upon the changes in the lamp turn-on time. That is, this study shows a technology that makes it possible to make various pulse shapes by turning on three flashlamps consecutively on a real-time basis with the aid of a PIC one-chip microprocessor, With this technique, the lamp turn-on delay time can be varied more diversely from 0 to 10 ms and the real-time control is possible with an external keyboard, enabling various pulse shapes. In addition, longer pulses can be more widely used for industrial processing and lots of medical purposes.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.