• 제목/요약/키워드: standard cell

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STANDARD OPERATING PROCEDURES OF HARD TISSUES SUCH AS FEMORAL HEAD, ALLOGRAFTS OBTAINED FROM LIVING DONORS (생존 기증자로부터 채취된 경조직(대퇴골두 등)의 조직은행 술식)

  • Lee, Eun-Young;Kim, Kyung-Won;Um, In-Woong;Ryu, Ju-Youn
    • Journal of the Korean Association of Oral and Maxillofacial Surgeons
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    • 제30권5호
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    • pp.406-413
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    • 2004
  • Progress in medical science and cell biology has resulted in the transplantation of human cells and tissues from on human into another, facilitating reproduction and the restoration of form and function, as well as enhancing the quality of life. For more than 40 years, society has recognized the medical and humanitarian value of donation and transplanting organs and tissues. The standard operating procedures of hard tissues reflect the collective expertise and conscientious efforts of tissue bank professionals to provide a foundation for the guidance of tissue banking activities. Procurement of allograft tissues from surgical bone donors is a part of tissue banking. During the past decades the use of bone allografts has become widely accepted for the filling of skelectal defects in a variety of surgical procedures. In particular in the field of orthopaedic and oral and maxillofacial surgery the demand for allografts obtained from either living or post-mortem donors has increased. Hospital-based tissue banks mainly retrieve allografts from living donors undergoing primary total hip replacement for osteoarthritis or hemi arthroplasty for hip fractures and orthgnatic surgery such as angle reduction. Although bone banks have existed for many years, the elements of organized and maintaining a hospital bone bank have not been well documented. The experience with a tissue bank at Korea Tissue Bank(KTB) between 2001 and 2004 provides a model of procurement, storage, processing, sterilization and documentation associated with such a facility. The following report describes the standard operating procedures of hard tissues such as femoral head obtained from living donors.

A Design of Multi-Standard LDPC Decoder for WiMAX/WLAN (WiMAX/WLAN용 다중표준 LDPC 복호기 설계)

  • Seo, Jin-Ho;Park, Hae-Won;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • 제17권2호
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    • pp.363-371
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    • 2013
  • This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

Design of Intra Prediction Circuit for HEVC and H.264 Multi-decoder Supporting UHD Images (UHD 영상을 지원하는 HEVC 및 H.264 멀티 디코더 용 인트라 예측 회로 설계)

  • Yu, Sanghyun;Cho, Kyeongsoon
    • Journal of the Institute of Electronics and Information Engineers
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    • 제53권12호
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    • pp.50-56
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    • 2016
  • This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.

Standard Transfer Free Energy of Sodium and Cupric Ions in Water-Acetylacetone Solvent System (물-아세틸아세톤 용매계에서 나트륨이온과 구리이온의 표준이동 자유에너지)

  • Lee Heung Lark;Park Jong-Taek
    • Journal of the Korean Chemical Society
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    • 제36권5호
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    • pp.632-637
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    • 1992
  • Standard transfer free energies of sodium and cupric perchlorates in water-acetylacetone solvent system have been determined by electromotive force measurements of galvanic cell and these energies of sodium and cupric ions in this solvent system have been evaluated by the tetrabutylammonium tetraphenylborate assumption as the extrathermodynamic procedure. Standard transfer free energy values of sodium and cupric ions from water to acetylacetone solvent were 5.09 and 4.16 kcal/mol at 25${\circ}C$, respectively. These values mean that acetylacetone is much weaker donor solvent to sodium and cupric ions than water. The standard transfer free energy value of cupric ion from water to mixture solvents which contain small amount of acetylacetone is changed by an unusual form. This is because of the chelate formation effect of acetylacetone to cupric ion.

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A Study on the Standard Cell and Its Enclosure (표준전지 및 표준전지 항온함 제작에 관한 연구)

  • Euijin Hwang;Hwashim Lee;Jinuk Lee;Hong Yol Kang
    • Journal of the Korean Chemical Society
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    • 제36권6호
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    • pp.857-863
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    • 1992
  • Acid type saturated Weston cells that can be used as the standard of electromotive force unit were constructed and their characteristics in a specially designed enclosure were evaluated. Cadmium sulfate was purified by recrystallization under vaccum. Mercurous sulfate with dispersed mercury and the exact composition of cadmium amalgam were obtained by means of electrolysis. The enclosure was constructed using a commercial circulator. Temperature of the enclosure was only drifted in the range of ${\pm}$5 mK in the case of extreme change of room temperature. The electromotive force of standard cells was measured over the temperature range of 5∼${\sim} 30^{\circ}C$. The standard deviation of the electromotive forces was about 1 ppm.

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Effects of acute normovolemic hemodilution on healing of gastric anastomosis in rats

  • Kim, Tae Yeon;Kim, Dong Won;Jeong, Mi Ae;Jun, Jong Hun;Min, Sung Jeong;Shin, Su-Jin;Ha, Tae Kyung;Choi, Dongho
    • Annals of Surgical Treatment and Research
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    • 제95권6호
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    • pp.312-318
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    • 2018
  • Purpose: Acute normovolemic hemodilution (ANH) is an autologous transfusion method, using blood collected during surgery, to reduce the need for allogeneic blood transfusion. ANH is controversial because it may lead to various complications. Among the possible complications, anastomotic leakage is one that would have a significant effect on the operation outcome. However, the relationship between ANH and anastomotic site healing requires additional research. Therefore, we conducted this prospective study of ANH, comparing it with standard intraoperative management, undergoing gastric anastomosis in rats. Methods: Sixteen Sprague-Dawley rats were randomly assigned to three groups: group A, surgery with ANH; group N, surgery with standard intraoperative management; and group C, sham surgery with standard intraoperative management. ANH was performed in group A animals by, removing 5.8-6.6 mL of blood and replacing it with 3 times as much crystalloid. All rats were enthanized on postoperative day 6, and histopathologic analyses were performed. Results: The mean hematocrit values, after hemodilution were 22.0% (range, 18.0%-29.0%), group A; 33.0% (29.0%-35.0%), group N; and 32.5% (29.0%-34.0%), group C. There were significant differences between groups A and N (P = 0.019, P = 0.009, P = 0.004, P = 0.039, and P = 0.027), and between groups N and C (P = 0.006, P = 0.027, P = 0.04, P = 0.008, and P = 0.009) with respect to inflammatory cell numbers, neovascularization, fibroblast numbers, edema and necrosis, respectively; there were no differences between groups A and N. Conclusion: In rat model, anastomotic complications did not increase in the ANH group, compared with the standard intraoperative management group.

An Analysis on rear contact for crystalline silicon solar cell (결정질 실리콘 태양전지에 적용하기 위한 후면전극 형성에 관한 연구)

  • Kwon, Hyukyong;Lee, Jaedoo;Kim, Minjung;Lee, Soohong
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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    • pp.91.1-91.1
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    • 2010
  • There are some methods for increasing efficiency of crystalline silicon solar cells. Among them, It is important to reduce the recombination loss of surface for high efficiency. In order to reduce recombination loss is a way to use the BSF(Back Surface Field). The BSF on the back of the p-type wafer forms a p+layer. so, it is prevented to act electrons of the p-area for the rear recombination. As a result, the leakage current is reduced and the rear-contact has a good Ohmic contact. therefore, open-circuit-voltage and Fill factor(FF) of solar cells are increased. This paper investigates the formation of rear contact process comparing Aluminum-paste(Al-paste) with Aluminum-Metal(99.9%). It is shown that the Aluminum-Metal provides high conductivity and low contact resistance of $21.35m{\Omega}cm$ using the Vacuum evaporation process but, it is difficult to apply the standard industrial process because high Vacuum is needed and it costs a tremendous amount more than Al-paste. On the other hand, using the Al-paste process by screen printing is simple for formation of metal contact and it is possible to produce the standard industrial process. however, it is lower than Aluminum-Metal(99.9) of conductivity because of including mass glass frit. In this study, contact resistances were measured by 4-point prove. each of contact resistances is $21.35m{\Omega}cm$ of Aluminum-Metal and $0.69m{\Omega}cm$ of Al-paste. and then rear contact have been analyzed by Scanning Electron Microscopy(SEM).

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Implementation and verification of H.264 / AVC Intra Predictor for mobile environment (모바일 환경에서의 H.264 / AVC를 위한 인트라 예측기의 구현 및 검증)

  • Yun, Cheol-Hwan;Jeong, Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • 제44권12호
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    • pp.93-101
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    • 2007
  • Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.

Design of a High-speed Decision Feedback Equalizer using the Constant-Modulus Algorithm (CMA 알고리즘을 이용한 고속 DFE 등화기 설계)

  • Jeon, Yeong-Seop;;Kim, Gyeong-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • 제39권4호
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    • pp.173-179
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    • 2002
  • This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

A Design of Low-Power 8-bit Microcontroller (저전력 8-비트 마이크로콘트롤러의 설계)

  • Lee, Sang-Jae;Jeong, Hang-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • 제39권2호
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    • pp.63-71
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    • 2002
  • This paper suggests a 8-bit RISC microcontroller, which has a 4-stage pipeline architecture. Many low-power design techniques that have been proposed by previous works are adopted into it. The proposed microcontroller consumes only 600㎼ per MIPS for 0.6 ${\mu}{\textrm}{m}$ CMOS process and even lower power of 70㎼ per MIPS for 0.25${\mu}{\textrm}{m}$ process. The RTL level design of this microcontroller is carried out using VHDL. The functional verification is thoroughly done at the gate level using 0.6${\mu}{\textrm}{m}$/0.25${\mu}{\textrm}{m}$ CMOS IDEC standard cell library. This microcontroller contains 7000 NAND gates on a 0.36$\textrm{mm}^2$ die using 0.25${\mu}{\textrm}{m}$ process. Finally the comparison of power consumption with other conventional microcontrollers is provided.