• Title/Summary/Keyword: source/drain

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Switching Characteristics of Amorphous GeSe TFT for Switching Device Application

  • Nam, Gi-Hyeon;Kim, Jang-Han;Jo, Won-Ju;Jeong, Hong-Bae
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.403-404
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    • 2012
  • We fabricated TFT devices with the GeSe channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is high. Based on the experiments, we draw the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

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Electrical Switching Characteristics of Thin Film Transistor with Amorphous Chalcogenide Channel

  • Nam, Gi-Hyeon;Kim, Jang-Han;Jeong, Hong-Bae
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.08a
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    • pp.280-281
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    • 2011
  • We fabricated the devices of TFT type with the amorphous chalcogenide channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is about 4 order. Based on the experiments, we contained the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

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Reduction of Transconduce in Saturation Region of Short Channel LDD(Lightly Doped Drain) NMOSFETs (짤은 채널 LDD(Lightly doped Drain)NMOSFET의 포화영역 Transconductance 감소)

  • 이명복;이정일;강광남
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.1
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    • pp.74-80
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    • 1990
  • The transconductance of short channel LDD MOSFETs in the saturation region (high Vd)has shown different characteristics from that of conventional device. The transconductance in saturation regime of short channel LDD MOSFETs is reduced from maximum value at higher gate voltage. This decline is analyzed as the velocity saturation effects of carrier at LDD region but accurate analytical expressions for the drain current Idsat and the transconductance Gmsat in the saturation regime are still not in existence. Recently the drain current dependence of parasitic source resistance Rs has been modeled from the velocity saturation of carriers in LDD region. In this study, we approximate that Rmsat that Rs is linearly dependent on the applied gate voltage. Analytical expressions for Idsat and Gmsat obtained from this approximation show the same general behavior as experimental results of short channel LDD NMOSFETs.

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Performance Optimization of LDMOS Transistor with Dual Gate Oxide for Mixed-Signal Applications

  • Baek, Ki-Ju;Kim, Yeong-Seuk;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.16 no.5
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    • pp.254-259
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    • 2015
  • This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (RON) and 50% drain conductance (gds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

A Scalable Bias-dependent P-HEMT Noise Model with Single Drain Current Noise Source (드레인 전류 잡음원만을 고려한 스케일링이 가능한 바이어스 의존 P-HEMT 잡음모델)

  • 윤경식
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.10A
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    • pp.1579-1587
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    • 1999
  • Bias-dependent noise models of $0.2\mu\textrm{m}$ gate length P-HEMT's which are scalable with gate width are proposed. To predict S-parameters of the P-HEMT's the intrinsic parameters except for $\tau$ subtracted the offsets introduced in this paper are normalized to the gate width and then scaled. The small-signal model parameters are expressed as fitting functions of the drain current to $\textrm{I}_{dss}$ ratio and gate width. In addition, to estimate accurately noise parameters the noise temperature $\textrm{T}_{g}$ of the intrinsic resistance, the equivalent noise conductance $\textrm{G}_{ni}$ of the gate current noise source, and the equivalent noise conductance $\textrm{G}_{no}$ of the drain current noise source are adopted as the noise model parameters. The extracted values of $\textrm{T}_{g}$ are nearly independent of drain current and gate width and their average is around the ambient temperature. The extracted values of $\textrm{G}_{ni}$ are small enough to be neglected to the circuit characteristics. From the comparison of the noise model with only $\textrm{G}_{no}$ and that having $\textrm{T}_{g}$, $\textrm{G}_{ni}$ and $\textrm{G}_{no}$ to the measured data it is fund that even the former model is in good agreement with the measured noise parameters. Thus, from a practical point of view the noise model having only the drain current noise source is confirmed as a scalable bias-dependent model.

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Optimization of Tunneling FET with Suppression of Leakage Current and Improvement of Subthreshold Slope (누설전류 감소 및 Subthreshold Slope 향상을 위한 Tunneling FET 소자 최적화)

  • Yoon, Hyun-kyung;Lee, Jae-hoon;Lee, Ho-seong;Park, Jong-tae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.713-716
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    • 2013
  • The device performances of N-channel Tunneling FET have been characterized with different intrinsic length between drain and gate($L_{in}$), drain and source doping, permittivity and oxide thickness when the total effective channel length is constant. N-channel Tunneling FET of SOI structure have been used in characterization. $L_{in}$ was from 30nm to 70nm, dose concentration of drain and source were from $2{\times}10^{12}cm^{-2}$ to $2{\times}10^{15}cm^{-2}$ and from $1{\times}10^{14}cm^{-2}$ to $3{\times}10^{15}cm^{-2}$, permittivity was from 3.9 to 29, and oxide thickness was from 3nm to 9nm. The device performances were characterized by Subthreshold slope(S-slope), On/off ratio, and leakage current. From the simulation results, the leakage current have been reduced for long $L_{in}$ and low drain doping. S-slope have been reduced for high source doping, high permittivity and thin oxide thickness. With considering the leakage current and S-slope, it is desirable that are long $L_{in}$, low drain doping, high source doping, high permittivity and thin oxide thickness to optimize device performance in n-channel Tunneling FET.

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A Study on the Current-Voltage Characteristics of a Short-Channel GaAs MESFET Using a New Linearly Graded Depletion Edge Approximation (선형 공핍층 근사를 사용한 단채널 GaAs MESFET의 전류 전압 특성 연구)

  • 박정욱;김재인;서정하
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.37 no.2
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    • pp.6-11
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    • 2000
  • In this paper, suggesting a new linearly -graded depletion edge approximation, the current-voltage characteristics of an n-type short-channel GaAs MESFET device has been analyzed by solving the two dimensional Poisson's equation in the depletion region. In this model, the expressions for the threshold voltage, the source and the drain ohmic resistance, and the drain current were derived. As a result, typical Early effect of a short channel device was shown and the ohmic voltage drop by source and drain contact resistances could be explained. Furthermore our model could analyze both the short-channel device and the long-channel device in a unified manner.

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The Experimental Research for the Use Characteristics of the Passive and Active type Domestic Solar Hot Water Systems (자연형 및 설비형 태양열 온수기의 이용특성에 대한 실험적 연구)

  • Lee, Dong-Won;Kwak, Hee-You
    • Journal of the Korean Solar Energy Society
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    • v.33 no.5
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    • pp.82-88
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    • 2013
  • There are the stirring test and drain test in the daily performance test to determine the thermal performance of a domestic solar hot water system. The drain test is a test that measures the discharge heating rate while drain the hot water from the top of the storage tank and supply the city water to the bottom of the tank. From the perspective of the user, this drain test is more effective than the stirring test. In this study, the thermal performance were compared through the drain test for a passive type and an active type domestic solar hot water systems consisting of the same storage tank and collectors. At this point, a passive type was used the horizontal storage tanks, and an active type was used vertical storage tank. In the drain test, when the hot water drained up to the reference hot water temperature, an active type which have vertical storage tank represents excellent daily performance than a passive type which have horizontal storage tank regardless of weather conditions. The reason for this is because the vertical storage tank is advantageous to thermal stratification in the tank. After the drain test, the residual heat for the horizontal storage tank was much more than the vertical storage tank, but in the next day the amount of discharged heat were less than the those of vertical storage tank neither. Thus, the solar water heating system which have horizontal storage tank should be adopted preheating control method rather than separate using control method when connected with auxiliary heat source device.

High Performance Silicon LDMOSFET for RF Power Amplifiers (RF 전력증폭기용 고성능 실리콘 LDMOSFET)

  • 신창희;김진호;권오경
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.695-698
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    • 2003
  • This paper presents a Si power LDMOSFET for power amplifiers in the 1.8-2.2GHz frequency range for the base station of personal communication systems. To improve the cut-off frequency, the proposed Si power LDMOSFET has small gate to drain capacitance by shielding the electric fields with extended source electrode and forming the field oxide structure in drain region. The proposed Si power LDMOSFET can be used for a power amplifier and it has 32% of power added efficiency and 39.5dBm of output power when the supply voltage is 28V and the operating frequency is 1.9GHz.

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