• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.2
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• pp.168-174
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• 2006

We investigated field-effect ion-transport devices based on carbon nanotubes by using classical molecular dynamics simulations under applied external force fields, and we present model schematics that can be applied to the nanoscale data storage devices and unipolar ionic field-effect transistors. As the applied external force field is increased, potassium ions rapidly flow through the nanochannel. Under low external force fields, thermal fluctuations of the nanochannels affect tunneling of the potassium ions whereas the effects of thermal fluctuations are negligible under high external force fields. Since the electric current conductivity increases when potassium ions are inserted into fullerenes or carbon nanotubes, the field effect due to the gate, which can modify the position of the potassium ions, changes the tunneling current between the drain and the source.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.395-395
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• 2007

We report on the fabrication of soluble pentacene-based thin-film transistors (TFTs) that consist of $NiO_x$, poly-vinyl phenol (PVP), and Ni for the source-drain (SID) electrodes, gate dielectric, and gate electrode, respectively. The $NiO_x$ SID electrodes of which the work function is well matched to that of soluble pentacene are deposited on a soluble pentacenechannel by sputter deposited of NiO powder and show a moderately low but still effective transmittance of ~65% in the visible range along with a good sheet resistance of ${\sim}40{\Omega}/{\square}$. The maximum saturation current of our soluble pentacene-based TFT is about $15{\mu}A$ at a gate bias of -40showing a high field effect mobility of $0.06cm^2/Vs$ in the dark, and the on/off current ratio of our TFT is about $10^4$. It is concluded that jointly adopting $NiO_x$ for the S/D electrodes and PVP for gate dielectric realizes a high-quality soluble pentacene-based TFT.

• Journal of IKEEE
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• v.25 no.1
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• pp.15-24
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• 2021

In this paper, 1700 V EPDT (Extended P+ shielding floating gate Double Trench) MOSFET structure, which has a smaller switching time and loss than CDT (Conventional Double Trench) MOSFET, is proposed. The proposed EPDT MOSFET structure extended the P+ shielding area of the source trench in the CDT MOSFET structure and divided the gate into N+ and floating P- polysilicon gate. By comparing the two structures through Sentaurus TCAD simulation, the on-resistance was almost unchanged, but Crss (Gate-Drain Capacitance) decreased by 32.54 % and 65.5 %, when 0 V and 7 V was applied to the gate respectively. Therefore, the switching time and loss were reduced by 45 %, 32.6 % respectively, which shows that switching performance was greatly improved.

• Journal of Chest Surgery
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• v.55 no.1
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• pp.81-84
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• 2022

Esophagectomy and esophageal reconstruction are commonly chosen as surgical options for esophageal cancer. However, prolonged untreated chyle leakage is associated with a poor prognosis. We report the case of a patient with refractory chylous ascites. To limit the ongoing fluid loss, we utilized the chylous ascites as an additional fluid source in a renal replacement therapy system. A continuous renal replacement therapy (CRRT) drainage system was modified to drain both the chylous ascites and venous blood. The ascites drainage rate was determined empirically and regulated by a dial-flow extension set. The CRRT mode was set to continuous venovenous hemodiafiltration and maintained for 7 days. After the patient was weaned from CRRT, ascites did not reaccumulate, and the patient's general condition improved dramatically. No infections related to the system occurred. This procedure temporarily alleviates symptoms and provides more time for alternative treatment strategies.

• Journal of Sensor Science and Technology
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• v.32 no.6
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• pp.386-390
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• 2023

Stiffness-engineered stretchable substrate technology has been widely used to produce stretchable displays, transistors, and integrated circuits because it is compatible with various flexible electronics technologies. However, the stiffness-engineering technology has never been applied to transistor-based stretchable strain sensors. In this study, we developed thin-film transistor-based strain sensors on stiffness-engineered stretchable substrates. We designed and fabricated strain-sensitive stretchable resistors capable of inducing changes in drain currents of transistors when subjected to stretching forces. The resistors and source electrodes of the transistors were connected in series to integrate the developed stretchable resistors with thin-film transistors on stretchable substrates by printing the resistors after fabricating transistors. The thin-film transistor-based stretchable strain sensors demonstrate feasibility as strain sensors operating under strains of 0%-5%. This strain range can be extended with further investigations. The proposed stiffness-engineering approach will expand the potential for the advancement and manufacturing of innovative stretchable strain sensors.

• Journal of Sensor Science and Technology
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• v.4 no.4
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• pp.29-40
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• 1995

In this paper, the noise equivalent cicuits that is necessary to the formulation of D.C. and noise characteristics, residual component and input capacitance so as to analyze on the noise factors of the SIT is proposed. The simplest noise equivalent circuit is the model representing the mechanism of the SIT and the measured values in this model were found as small as the values of the shot-noise. In the source resistance inserted equivalent circuit is conformed that the shot-noise will be reduced by the negative-feedback effect of the source resistance. In oder to analyze the correct noise reduction factor, I proposed the equivalent circuit which the formulas of the source and drain resistance was induced. In the experiment which affirm the equivalent circuits, the influence of the signal source resistance and output load resistance on the residual component is small and the residual component can be expressed by the equivalent input noise resistance. Moreover, the input capacitance is 13.6 pF when the load resistance is $0{\Omega}$ and the capacitance which does not concern with the SIT operation directly, that is, gate wire etc, is 10pF or so.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.95-102
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• 2001

Nano-scale gate length MOSFET devices require extremely shallow source/drain eftension region with junction depth of 20∼30nm. In this work, 20nm $n^{+}$-p junctions that are realized by using this $As_{2}^{+}$ low energy ($\leq$10keV) implantation show the lower sheet resistance of the $1.0k\Omega$/$\square$ after rapid thermal annealing process. The $As_{2}^{+}$ implantation and RTA process make it possible to fabricate the nano-scale NMOSFET of gate length of 70nm. $As_{2}^{+}$ 5 keV NMOSFET shows a small threshold voltage roll-off of 60mV and a DIBL effect of 87.2mV at 100nm gate length devices. The electrical characteristics of the fabricated devices with the heavily doped and abrupt $n^{+}$-p junctions ($N_{D}$〉$10^{20}$$cm^{-3}$, $X_{j}$$\leq$20nm) suggest the feasibility of the nano-scale NMOSFET device fabrication using the $As_{2}^{+}$ low energy ion implantation.

• Journal of electromagnetic engineering and science
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• v.1 no.1
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• pp.73-77
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• 2001

We studied the fabrication of GaAs-based pseudomorphic high electron mobility transistors(PHEMT`s) for the purpose of millimeter- wave applications. To fabricate the high performance GaAs-based PHEMT`s, we performed the simulation to analyze the designed epitaxial-structures. Each unit processes, such as 0.1 m$\mu$$\Gamma$-gate lithography, silicon nitride passivation and air-bridge process were developed to achieve high performance device characteristics. The DC characteristics of the PHEMT`s were measured at a 70 $\mu$m unit gate width of 2 gate fingers, and showed a good pinch-off property ($V_p$= -1.75 V) and a drain-source saturation current density ($I_{dss}$) of 450 mA/mm. Maximum extrinsic transconductance $(g_m)$ was 363.6 mS/mm at $V_{gs}$ = -0.7 V, $V_{ds}$ = 1.5 V, and $I_{ds}$ =0.5 $I_{dss}$. The RF measurements were performed in the frequency range of 1.0~50 GHz. For this measurement, the drain and gate voltage were 1.5 V and -0.7 V, respectively. At 50 GHz, 9.2 dB of maximum stable gain (MSG) and 3.2 dB of $S_{21}$ gain were obtained, respectively. A current gain cut-off frequency $(f_T)$ of 106 GHz and a maximum frequency of oscillation $(f_{max})$ of 160 GHz were achieved from the fabricated PHEMT\\`s of 0.1 m$\mu$ gate length.h.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.169-169
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• 2010

As display industry requires various applications for future display technology, which can guarantees high level of flexibility and transparency on display panel, oxide semiconductor materials are regarded as one of the best candidates. $InGaZnO_4$(IGZO) has gathered much attention as a post-transition metal oxide used in active layer in thin-film transistor. Due to its high mobility fabricated at low temperature fabrication process, which is proper for application to display backplanes and use in flexible and/or transparent electronics. Electrical performance of amorphous oxide semiconductors depends on the resistance of the interface between source/drain metal contact and active layer. It is also affected by sheet resistance on IGZO thin film. Controlling contact/sheet resistance has been a hot issue for improving electrical properties of AOS(Amorphous oxide semiconductor). To overcome this problem, post-annealing has been introduced. In other words, through post-annealing process, saturation mobility, on/off ratio, drain current of the device all increase. In this research, we studied on the relation between device's resistance and post-annealing temperature. So far as many post-annealing effects have been reported, this research especially analyzed the change of electrical properties by increasing post-annealing temperature. We fabricated 6 main samples. After a-IGZO deposition, Samples were post-annealed in 5 different temperatures; as-deposited, $100^{\circ}C$, $200^{\circ}C$, $300^{\circ}C$, $400^{\circ}C$ and $500^{\circ}C$. Metal deposition was done on these samples by using Mo through E-beam evaporation. For analysis, three analysis methods were used; IV-characteristics by probe station, surface roughness by AFM, metal oxidation by FE-SEM. Experimental results say that contact resistance increased because of the metal oxidation on metal contact and rough surface of a-IGZO layer. we can suggest some of the possible solutions to overcome resistance effect for the improvement of TFT electrical performances.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.245-245
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• 2012

차세대 디스플레이로 각광받고 있는 AMOLED에 대한 관심이 높아짐에 따라 구동 소자의 연구가 활발히 이루어지고 있다. 산화물 반도체 박막 트랜지스터는 비정질 실리콘 박막 트랜지스터에 비해 100 $cm^2$/Vs 이하의 높은 이동도와 우수한 전기적 특성으로 AMOLED 구동 소자로서 학계에서 입증되어왔고, 현재 여러 기업에서 산화물 반도체를 이용한 박막 트랜지스터 제작 연구가 활발히 이루어지고 있다. 본 연구는 열처리 조건을 가변하여 제작한 산화물 반도체 박막 트랜지스터의 전기적 특성 분석을 목적으로 한다. 실리콘 기판에 oxidation 공정을 이용하여 SiO2 100 nm, DC스퍼터링을 이용하여 ITZO (Indium-Tin-Zinc Oxide) 산화물 반도체 박막 50 nm, 증착된 산화물 반도체 박막의 열처리 후, evaporation을 이용하여 source/drain 전극 Ag 150 nm 증착하여 박막 트랜지스터를 제작하였다. 12 sccm의 산소유량, 1시간의 열처리 시간에서 열처리 온도 $400^{\circ}C$, $200^{\circ}C$의 샘플은 각각 이동도 $29.52cm^2/V{\cdot}s$, $16.15cm^2/V{\cdot}s$, 문턱전압 2.61 V, 6.14 V, $S{\cdot}S$ 0.37 V/decade, 0.85 V/decade, on-off ratio 5.21 E+07, 1.10 E+07이었다. 30 sccm의 산소유량, 열처리 온도 $200^{\circ}C$에서 열처리 시간 1시간, 1시간 30분 샘플은 각각 이동도 $12.27cm^2/V{\cdot}s$, $10.15cm^2/V{\cdot}s$, 문턱전압 8.07 V, 4.21 V, $S{\cdot}S$ 0.89 V/decade, 0.71 V/decade, on-off ratio 4.31 E+06, 1.05 E+07이었다. 산화물 반도체의 열처리 효과 분석을 통하여 높은 열처리 온도, 적은 산소의 유량, 열처리 시간이 길수록 이동도, 문턱전압, $S{\cdot}S$의 산화물 박막 트랜지스터 소자의 전기적 특성이 개선되었다.