• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• 대한전자공학회논문지SD
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• 제41권7호
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• pp.1-6
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• 2004

나노 급 소자에서의 성능이 유효 채널 길이에 대하여 더욱 민감하게 되므로 정확한 유효 채널 길이의 추출이 중요하다. 본 논문에서는 100 ㎚ 이하의 MOSFET에서 유효 채널 길이를 추출하기 위하여 새로운 정전용량-전압(Capacitance-Voltage) 방법을 제안하였다. 제안한 방법에서는 게이트와 소스와 드레인 사이의 정전용량(C/sub gsd/)를 측정하여 유효 채널 길이를 추출하였다. 그리고 추출된 유효 채널 길이와 기존의 1/β 과 Terada 방법 그리고 다른 정전용량-전압 방법의 추출된 유효 채널 길이의 결과들과 비교하여 본 논문에서 제안한 추출방법이 100 ㎚ 이하 크기의 MOSFET의 유효 채널 길이를 추출함에 타당함을 증명하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

• 한국의류산업학회지
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• 제5권5호
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• pp.539-544
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• 2003

The purpose of this study is to research source of soil which is available for non-detergent course, and to develop optimum non-detergent course of washing machine for water soluble soil. The water soluble soil such as grape juice, soy bean paste and soy sauce were easily removed from the fabric but the oil soluble soils such as sesame oil and steak sauce were insurfficiently removed in washing solution without detergent. In the absence of detergent, amount of residual soils increased linearly with increasing number of soiling and washing. To search optimum conditions of washing for non-detergent course, the effect of temperature, washing time and washing method on detergency of soil in non-detergent washing solution was examined. The optimum washing temperature and washing time for non-detergent course were about $40^{\circ}C$, and 7 minutes, respectively. And in the non-detergent washing solution, midterm drain-resupply of water during washing process was good for removal of water soluble soil.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.52-62
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• 2004

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.312-317
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• 2015

In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source ($C_{gs}$) and gate-to-drain ($C_{gd}$) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency ($f_T$) and maximum-oscillation frequency ($f_{max}$) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.

• 한국전기전자재료학회논문지
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• 제20권5호
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• 한국전기전자재료학회논문지
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• 제25권4호
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• pp.304-308
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• 2012

Transparent thin film transistors (TTFT) were fabricated using the rf magnetron sputtered ZnO-$SnO_2$ films as active layers. A ceramic target whose Zn atomic ratio to Sn is 2:1 was employed for the deposition of ZnO-$SnO_2$ films. To study the post-annealing effects on the properties of TTFT, ZnO-$SnO_2$ films were annealed at $200^{\circ}C$ or $400^{\circ}C$ for 5 min before In deposition for source and drain electrodes. Oxygen was added into chamber during sputtering to raise the resistivity of ZnO-$SnO_2$ films. The effects of oxygen addition on the properties of TTFT were also investigated. 100 nm $Si_3N_4$ film grown on 100 nm $SiO_2$ film was used as gate dielectrics. The mobility, $I_{on}/I_{off}$, interface state density etc. were obtained from the transfer characteristics of ZnO-$SnO_2$ TTFTs.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.99-99
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• 2010

Recently, amorphous transparent oxide semiconductors (TOS) have been widely studied for many optoelectronic devices such as AM-OLED (active-matrix organic light emitting diodes). The TOS TFTs using a-IGZO channel layers exhibit a high electron mobility, a smooth surface, a uniform deposition at a large area, a high optical transparency, a low-temperature fabrication. In spite of many advantages of the sputtering process such as better step coverage, good uniformity over large area, small shadow effect and good adhesion, there are not enough researches about characteristics of a-IGZO thin films. In this study, therefore, we focused on the electrical properties of a-IGZO thin films as a channel layer of TFTs. TFTs with the a-IGZO channel layers and Y2O3 gate insulators were fabricated. Source and drain layers were deposited using ITO target. TFTs were deposited on unheated non-alkali glass substrates ($5cm{\times}5cm$) with a sintered ceramic IGZO disc (3 inch $\varnothing$, 5mm t), Y2O3 disc (3 inch $\varnothing$, 5mm t) and ITO disc (3 inch $\varnothing$, 5mm t) as a target by magnetron sputtering method. The O2 gas was used as the reactive gas. Deposition was carried out under various sputtering conditions to investigate the effect of sputtering process on the characteristics of a-IGZO thin films. Correlation between sputtering factors and electronic properties of the film will be discussed in detail.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.204-204
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• 2010

본 연구에서는 Glass 기판 위에 우수한 광 투과도를 갖는 ZnO 기반의 Thin Film Transistor (TFT)를 제작하였으며, 이에 대한 전기적 및 광학적 특성을 분석하였다. 소자 구조의 제작은 Maskless Aligner를 이용한 Optical lithograph법을 이용하였다. 채널층은 ZnO로 하였고 Source/Drain 영역은 GaZnO로 하여 전체구조가 ZnO 기반의 homogeneity를 유지하게 하였다. 이때 Gate 절연막은 Bi1.5Zn1Nb1.5O7와 SiO2 두가지 종류로 하여 각각의 특성을 비교하였다. 본연구에서 TFT구조의 각 층은 모두 r. f. 마그네트론 스퍼터법으로 증착하였다. 제작된 TFT들은 채널층 및 절연막 형성 등에 관여된 세부적 실험변수의 변화에 관계없이 약 75% 이상의 우수한 광투과도 특성을 보였다. 전기적 특성 평가에서, 제작된 TFT들은 전반적으로 비교적 낮은 문턱전압과 높은 이동도를 보였다. 하지만, 트랜지스터의 전기적 전송 특성의 주요 인자들인 채널-이동도, 스위칭, 누설 및 이력 등은 ZnO 채널층 혹은 Bi1.5Zn1Nb1.5O7 절연막 형성 시 주입되는 O2 가스의 분압에 의존하는 것이 관측되었다. 이를 통하여 트랜지스터의 각 세부 영역의 구조 및 형성 조건이 트랜지스터의 전기적 특성에 미치는 영향과 상관관계에 대하여 논의한다.