• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.266-272
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• 2009

In the present work three dimensional process and device simulations were employed to study the performance variations with RTA. It is observed that with the increase in RTA temperature, the arsenic dopants from the source /drain region diffuse laterally under the spacer region and simultaneously acceptors (Boron) are redistributed from the central axis region of the fin towards the Si/SiO2 interface. As a consequence both drive current and peak cut-off frequency of an n-FinFET are observed to improve with RTA temperatures. Volume inversion and hence the flow of carries through the central axis region of the fin due to reduced scattering was found behind the performance improvements with increasing RTA temperature.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.323-324
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• 2009

We investigated the electrical properties of tris-isopropylsilylethynyl (TIPS)-pentacene organic thin-film transistors (OTFTs) employing Ni/Ag source/drain electrodes. The gap height between the gate insulator and S/D electrode was controlled by changing the thickness of Ag under-layer(20, 30, 40 and 50nm). After evaporating the Ni under-layer, TIPS pentacene channel material was dropping the gap between the gate insulator and SID electrodes. The electrical proprieties of OTFT such as filed-effect mobility, on/off ratio, threshold voltage and subthreshold slope were significantly influenced by the gap height.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.279-280
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• 2009

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.

• 대한전자공학회논문지
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• 제18권4호
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• pp.43-48
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• 1981

CdSe 반수체와 SiO유전체를 사용하여 진공증착방법으로 박막트랜지스터를 제조하고 반도체의 두께 및 드레인-소오스간의 채널길이 변화가 박막트랜지스터의 특성에 미치는 경향을 조사하였다. 반도체의 두께를 1500Å으로 하고 채널길이를 40μm으로 제조한 TFT가 가장 좋은 특성을 나타내었다. 이 특성을 MOSFET의 관계식에 적용하여 이로부터 Cd Se반도체의 캐리어 이동도는 115㎠/V·sec였고 활성화 에너지는 0.13ev였다.

• 센서학회지
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• 제27권3호
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• pp.150-155
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• 2018

Three different structures of GaN MOSFETs with trap distributions, trap levels, and densities were simulated, and its results were analyzed. Two of them are Schottky barrier MOSFETs(SB-MOSFETs): one with a p-type GaN body while the other is in the accumulation mode MOSFET with an undoped GaN body and regrown source/drain. The trap levels, distributions and densities were considered based on the measured or calculated properties. For the SB-MOSFET, the interface trap distribution affected the threshold voltage significantly, but had a relatively small influence on the subthreshold swing, while the bulk trap distribution affects the subthreshold swing more.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2010년도 추계 학술발표회
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• pp.144-169
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• 2010

In 2002, property loss caused by failure or leakage of existing river levee structures was about 1.8 trillion in Korean Won, and furthermore in which damages of river structures are getting more severe due to characteristics of extremely extraordinary rain such as torrential rain in the locality or guerrilla heavy rain. In this regards, this paper collects and analyzes those damage records and costs for repair by statistic method, and moreover categorizes the causes of failure, erosion and overtopping of levee structures in large and small scale rivers threatened frequently by typhoon and heavy rainfall. It is believed that the results from the analyses can be used as a basic source in developing criteria of standards for design, construction, maintenance and inspection(or diagnosis) of hydraulic structures such as levee and drain conduit.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.25-26
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• 2011

In this paper, we investigated the effect of various annealing processes on the electrical characteristics of oxide thin film transistors (TFTs). When we annealed the TFT devices before and after source/drain (S/D) process, we could observe the different electrical characteristics of oxide TFTs. When we annealed the TFTs after deposition of transparent indium zinc oxide S/D electrodes, the annealing process decreased the contact resistance but increased the resistivity of S/D electrodes. The field effect mobility, subthreshold slope and threshold voltage of the oxide TFTs annealed before and after S/D process were 5.83 and 4.47 $cm^2$/Vs, 1.20 and 0.82 V/dec, and 3.92 and 8.33 V respectively. To analyze the differences, we measured the contact resistances and the carrier concentrations using transfer length method (TLM) and Hall measurement.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.126-126
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• 2003

유기트랜지스터에 관한 연구는 1980년 이후부터 시작되었으나 근래에 들어 전 세계적으로 본격적인 연구가 진행되고 있다. 제작공정이 간단하고 비용이 저렴하며 충격에 의해 깨지지 않고 구부리거나 접을 수 있는 전자 회로 기판이 미래의 산업에 필수적인 요소가 될 것으로 예상되고 있으며 이러한 요구를 충족시킬 수 있는 유기트랜지스터의 개발은 아주 중요한 연구분야로 대두되고 있다. 본 연구에서는 표면처리에 따른 contact angle, I-V 특성곡선, 표면 morphology 등의 결과로부터 dry cleaning 한 것이 wet cleaning한 것보다 왜 좋은지를 논하고자 한다. 먼저 N-type SiO$_2$ 기판을 이용하여 back면의 oxide층을 제거한 후, back gate용으로 사용하기 위하여 sputtering장치로 Au/Cr을 증차하였다. 그리고 기판에 앞면을 photolithography 공정을 이용하여 Au/Cr를 1000$\AA$ 증착 하여 source-, drain-eldctrode를 제조하였다. 그리고 SiO$_2$ 기판의 표면처리를 달리하여 그 위에 유기박막을 증착하여 특성을 비교하였다.

• Transactions on Electrical and Electronic Materials
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• 제9권4호
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• pp.151-155
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• 2008

Using pentacene field effect transistors (FETs) with Au source and drain electrodes, electron injection from the Au electrodes into the pentacene was investigated. The capacitance-voltage (C-V) and optical second harmonic generation (SHG) measurements were employed. Electron injection from the Au electrodes was suggested by the hysteresis behavior with the C-V characteristics and slowly decaying SHG signal under DC biasing, A mechanism of hole-injection assisted by trapped electrons is proposed. To confirm electron injection process, light-emitting behavior under the application of AC applied voltage was observed.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1305-1307
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• 2007

We show that the electrical properties of organic thinfilm transistors(OTFTs) can be enhanced by controlling the morphology of interface between screen printed electrodes and gate dielectrics. Modified surface of the insulator layer($SiO_2$) affect on the interface energy of electrode on $SiO_2$ layer. Contact angle measurement and FT-IR spectrum shows that the interface is properly modified. OTFTs device with high efficiency has been realized through modification of interface layer.