• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.3
• /
• pp.169-181
• /
• 2011

In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: $g_{m1}$, $g_{m2}$, $g_{m3}$, and figure-of-merit (FOM) metrics; $V_{IP2}$, $V_{IP3}$, IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth ($X_j$) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.33 no.1
• /
• pp.78-82
• /
• 2020

In this study, MOSFETs fabricated on Si-doped, MBE-grown β-Ga₂O₃ are demonstrated. A Si-doped Ga₂O₃ epitaxial layer was grown on a Fe-doped, semi-insulating 1.5 cm × 1 cm Ga₂O₃ substrate using molecular beam epitaxy (MBE). The fabricated devices are circular type MOSFETs with a gate length of 3 ㎛, a source-drain spacing of 20 ㎛, and a gate width of 523 ㎛. The device exhibited a good pinch-off characteristic, a high on-off drain current ratio of approximately 2.7×10⁹, and a high breakdown voltage of 1,080 V, which demonstrates the potential of Ga₂O₃ for power device applications including electric vehicles, railways, and renewable energy.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.2
• /
• pp.156-163
• /
• 2008

We proposed a new $p^+/n^+$ gate locally-separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of $n^+$ poly-Si gate ($L_s$), the material filling the trench, and the width and length of the trench at a given gate length ($L_g$). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent $I_{off}$ suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable $L_s/L_g$ and channel fin width ($W_{cfin}$) at given $L_gs$ of 30 nm, 40 nm, and 50 nm.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.66 no.10
• /
• pp.1494-1498
• /
• 2017

In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage ($V_{dd}$) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high $I_{on}/I_{off}$ ratios are major factors that enable the excellent operation of the logic gate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.04b
• /
• pp.45-48
• /
• 2002

Poly(3-hexylthiophene) or P3HT based organic thin film transistor (OTFT) array was fabricated on flexible poly carbonate substrates and the electrical characteristics were investigated. As the gate dielectric, a dual layer structure of polyimide-$SiO_2$ was used to improve the roughness of $SiO_2$ surface and further enhancing the device performance and also source-drain electrodes were $O_2$ plasma treated for improvement of the electrical properties, such as drain current and field effect mobility. For the active layer, polymer semiconductor, P3HT layer was printed by contact-printing and spin-coating method. The electrical properties of OTFT devices printed by both methods were evaluated for the comparison. Based on the experiments, P3HT-based OTFT array with field effect mobility of 0.02~0.025 $cm^{2}/V{\cdot}s$ and current modulation (or $I_{on}/I_{off}$ ratio) of $10^{3}\sim10^{4}$ was fabricated.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.12
• /
• pp.179-183
• /
• 2012

The random dopant fluctuation (RDF) effects of tunneling field-effect transistors (TFETs) have been observed by using atomistic 3-D device simulation. Due to extremely low body doping concentration, the RDF effects of TFETs have not been seriously investigated. However, in this paper, it has been found that the randomly generated and distributed source dopants increase the variation of threshold voltage ($V_{th}$), drain induced current enhancement (DICE) and subthreshold slope (SS) of TFETs. Also, some ways of relieving the RDF effects of TFETs have been presented.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.2
• /
• pp.110-119
• /
• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.10
• /
• pp.54-61
• /
• 2011

In this paper, a simple analytical model for deriving the I-V characteristics of a cylindrical surrounding gate SOI MOSFET with intrinsic silicon core is suggested. The Poisson equation in the intrinsic silicon core and the Laplace equation in the gate oxide layer are solved analytically. The surface potentials at both source and drain ends are obtained by means of the bisection method. From them, the surface potential distribution is used to describe the I-V characteristics in a closed-form. Simulation results seem to show the dependencies of the I-V characteristics on the various device parameters and applied bias voltages within a range of satisfactory accuracy.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.7-12
• /
• 2008

In this study, the wide width effect that the increasing rate of drain current and the value of cutoff frequency decrease with larger finger number is observed. For modeling this effect, an improved SPICE MOSFET RF model that finger number-independent external source resistance is connected to a conventional BSIM3v3 RF model is developed. Better agreement between simulated and measured drain current and cutoff frequency at different finger number is obtained for the improved model than the conventional one, verifying the accuracy of the improved model for $0.13{\mu}m$ multi-finger MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.1
• /
• pp.43-47
• /
• 2013

In this work, we report extraction of the density-of-states (DOS) in polymer-based organic thin film transistors through the multi-frequency C-V spectroscopy. Extracted DOS is implemented into a TCAD simulator and obtained a consistent output curves with non-linear characteristics considering the contact resistance effect. We employed a Schottky contact model for the source and drain to fully reproduce a strong nonlinearity with proper physical mechanisms in the output characteristics even under a very small drain biases. For experimental verification of the model and extracted DOS, 2 different OTFTs (P3HT and PQT-12) are employed. By controlling the Schottky contact model parameters in the TCAD simulator, we accurately reproduced the nonlinearity in the output characteristics of OTFT.