Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Analytical Model for Deriving the I-V Characteristics of an Intrinsic Cylindrical Surrounding Gate MOSFET

Intrinsic Cylindrical/Surrounding Gate SOI MOSFET의 I-V 특성 도출을 위한 해석적 모델

  • Woo, Sang-Su (School of Electronic & Electrical Eng., Hongik Univ.) ;
  • Lee, Jae-Bin (School of Electronic & Electrical Eng., Hongik Univ.) ;
  • Suh, Chung-Ha (School of Electronic & Electrical Eng., Hongik Univ.)
  • 우상수 (홍익대학교 전자전기공학부) ;
  • 이재빈 (홍익대학교 전자전기공학부) ;
  • 서정하 (홍익대학교 전자전기공학부)
  • Received : 2011.03.16
  • Accepted : 2011.10.21
  • Published : 2011.10.25
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a simple analytical model for deriving the I-V characteristics of a cylindrical surrounding gate SOI MOSFET with intrinsic silicon core is suggested. The Poisson equation in the intrinsic silicon core and the Laplace equation in the gate oxide layer are solved analytically. The surface potentials at both source and drain ends are obtained by means of the bisection method. From them, the surface potential distribution is used to describe the I-V characteristics in a closed-form. Simulation results seem to show the dependencies of the I-V characteristics on the various device parameters and applied bias voltages within a range of satisfactory accuracy.

본 논문에서는 intrinsic-body cylindrical/surrounding gate SOI MOSFET의 I-V 특성 도출을 위한 간단한 해석적 모델을 제시하였다. Intrinsic 실리콘 채널 영역에서의 Poisson 방정식과 gate oxide 내에서의 Laplace 방정식을 해석적으로 풀어 소스와 드레인 양단 끝에서의 표면 전위 분포를 bisection method를 이용하여 구하였다. 구해진 표면 전위를 바탕으로 closed-form의 I-V 특성 식을 도출하였다. 도출된 I-V 특성 표현 식을 모의 실험한 결과, 소자의 parameter와 가해진 bias 전압에 대한 비교적 정확한 의존성을 확인할 수 있었다.

Keywords

References

  1. Jin He, Xing Zhang, Ganggang Zhang, Mansun Chan, Yangyuan Wang, "A carrier-based analytic DCIV model for long channel undoped cylindrical surrounding-gate MOSFETs", Solid-State Electronics, vol 50, pp. 416, 2006. https://doi.org/10.1016/j.sse.2006.01.015
  2. F. Djeffal, M.A. Abdi, Z. Dibi, M. Chahdi, A. Benhaya, "A neural approach to study the scaling capability of the undoped Double-Gate and cylindrical Gate All Around MOSFETs", Material Science & Engineering, vol. 147, pp. 239, 2008. https://doi.org/10.1016/j.mseb.2007.08.034
  3. T.K. Chiang, "A New Two-dimensional Analytical Model for Threshold Voltage in Undoped Surrounding-gate MOSFETs", IEEE Conferences, pp. 1234, 2006.
  4. Palash Roy, Binit Syamal, N. Mohankumar, C. K. Sarkar, "Modeling of Threshold Voltage for Undoped Surrounding Gate MOSFET: A Gaussian Approach", IEEE Conferences, pp. 1, 2009.
  5. Hamdy Abd-Elhamid, Benjamin Iniguez, David Jimenez, Jaume Roig, Josep Pallares, Lluis F. Marsal, "Two-dimensional analytical threshold voltage roll-off and subthreshold swing models for undoped cylindrical gate all around MOSFET", Solid-State Electronics, vol. 50, pp. 805, 2006. https://doi.org/10.1016/j.sse.2006.04.020
  6. Jin He, Yadong Tao, Feng Liu, Jie Feng, Shengqi Yang, "Analytic channel potential solution to the undoped surrounding-gate MOSFETs", Solid-State Electronics, vol. 51, pp. 802, 2007. https://doi.org/10.1016/j.sse.2007.02.035
  7. Sang-Hyun Oh, Don Monroe, J. M. Hergenrother, "Analytic Description of Short-Channel Effects in Fully-Depleted Double-Gate and Cylindrical, Surrounding-Gate MOSFETs", IEEE ELECTRON DEVICE LETTERS, vol. 21(9), pp. 445, 2000. https://doi.org/10.1109/55.863106
  8. Wei Bian, Jin He, Yu Chen, Yue Fu, Rui Zhang, Lining Zhang, Mansun Chan, "Complicated Subthreshold Behavior of Undoped Cylindrical Surrounding-Gate MOSFETs" IEEE Conferences, pp. 589, 2007.
  9. D. Jimenez, B. Iniguez, J. Sune, L. F. Marsal, J. Pallares, J. Roig, D. Flores, "Continuous Analytic I-V Model for Surrounding-Gate MOSFETs", IEEE ELECTRON DEVICE LETTERS, vol. 25(8), pp. 571, 2004. https://doi.org/10.1109/LED.2004.831902
  10. S. H. Lin, X. Zhou, G. H. See, Z. M. Zhu, G. H. Lim, C. Q. Wei, G. J. Zhu, Z. H. Yao, X. F. Wang, M. Yee, L. N. Zhao, Z. F. Hou, L. K. Ang, T. S. Lee, W. Chandra, "A Rigorous Surface-Potential-Based I-V Model for Undoped Cylindrical Nanowire MOSFETs", IEEE Conferences, pp. 889, 2007.
  11. Oana Moldovana, Benjamin Iniguez, David Jimenez, Jaume Roig, "New Explicit Charge and Capacitance Models for Undoped Surrounding Gate MOSFETs", IEEE Conferences, pp. 123, 2007.
  12. Christopher P. Auth, James D. Plummer, "Scaling Theory for Cylindrical, Fully-Depleted, Surrounding-Gate MOSFET''s", IEEE ELECTRON DEVICE LETTERS, vol. 18(2), pp. 74, 1997. https://doi.org/10.1109/55.553049
  13. C. H. Suh, "Two-Dimensional Analytical Model for Deriving the Threshold Voltage of a Short Channel Fully Depleted Cylindrical/Surrounding Gate MOSFET", 대한전자공학회, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 제11권 제2호, 111-120쪽, 2011년. https://doi.org/10.5573/JSTS.2011.11.2.111
  14. Jin He, Xing Zhang, Ganggang Zhang, Mansun Chan, Yangyuan Wang, "A Complete Carrier-Based Non-Charge-Sheet Analytic Theory for Nano-Scale Undoped Surrounding-Gate MOSFETs", IEEE Computer Society, vol. 6, pp. 120, 2006.
  15. Wei Bian, Jin He, Yadong Tao, Min Fang, Jie Feng, "An Analytic Potential-Based Model for Undoped Nanoscale Surrounding-Gate MOSFETs", IEEE Trans. Electron Devices, vol. 54(9), pp. 2293, 2007. https://doi.org/10.1109/TED.2007.902866
  16. 장은성, 오영해, 서정하, "Short-Channel Intrinsic-Body SDG SOI MOSFET의 문턱전압 도출을 위한 해석적 모델", 대한전자공학회 논문지, SD편, 제46권 제11호 (통권 제389호), 1-7쪽, 2009년.