• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.04a
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• pp.65-66
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• 2008

The realization and origin of p-type ZnO are main issue for photoelectronic devices based on ZnO material. N-doped and nominally undoped p-type ZnO films were achieved on silicon (100) and homo-buffer layers by RF magnetron sputtering and post in-situ annealing. The undoped film shows high hole mobility of 1201 $cm^2V^{-1}s^{-1}$ and low resistivity of $0.0454\Omega{\cdot}cm$ with hole concentration of $1.145\times10^{17}cm^{-3}$. The photoluminescence(PL) spectra show the emissions related to FE, DAP and defects of $V_{Zn}$, $V_O$, $Zn_O$, $O_i$ and $O_{Zn}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.25-28
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• 2001

Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. Without applying the conventional complex reverse moat process, CMP(Chemical Mechanical Polishing) has established the Process simplification. However, STI-CMP process have various defects such as nitride residue, torn oxide defect, damage of silicon active region, etc. To solve this problem, in this paper, we discussed to determine the control limit of process, which can entirely remove oxide on nitride from the moat area of high density as reducing the damage of moat area and minimizing dishing effect in the large field area. We, also, evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions.

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.23-24
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• 1995

기존의 웨이퍼 박막속에 절연박막이 삽입된 SOI(Silicon On Insulator) 웨이퍼 구조와 관련한 반도체 기판 재료가 커다른 관심을 끌어 왔으나, SOI 평가기술은 아직까지 체계적으로 확립된 것이 없으며, DLTS(Deep Level Transient Spectroscopy) 등을 이용한 전기적 평가는 거의 이루어지지 않은 상태이다. 본 연구에서는 직접접합된 웨이퍼를 약 10um내외의 활성화층을 형성시킨 6인치 P-형 SOI 웨이퍼를 제작하여 DLTS로 측정, 평가를 하였고, DLTS 측정후 관찰될 수 있는 에어지 트랩(Energy Trap)과 후속 열처리에서의 트랩의 변화등을 관찰하여, 후속 열처리조건에 따른 접합된 SOI 웨이퍼 계면의 안정화된 조건을 확보하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.838-843
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• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.6-6
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• 2010

This paper describes that single crystal cubic silicon (3C-SiC) films have been deposited on carbonized Si(100) substrate using hexamethyldisilane(HMDS, $Si_2(CH_3)_6$) as a safe organosilane single-source precursor and a nonflammable mixture of Ar and $H_2$ gas as the carrier gas by APCVD at $1280^{\circ}C$. The 3C-SiC film had a very good crystal quality without defects due to viods, a very low residual stress.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1998.03a
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• pp.196-202
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• 1998

Recently, developments in the frontier industry have brought a rapid increase in the use of brittle materials such as silicon wafer, ferrite, sintered carbide, MgO single crystal and die steel. Because of high hardness and brittleness the cracking and chipping are apt to generate in the grinding of brittle materials, but have replaced gradually the high precision grinding. In this study, the optimum system of in-process electrolytic dressing controlled by computer was developed for improving the defects, and could maintain the optimum dressing condition at all times. The control of in-process dressing was simplified using this system, was able to maintain a stable dressing current and was unrelated to the change of dressing condition according to the variation of gap and oxide layer. Therefore, the optimum in-process electrolytic dressing system was constructed and the analysis of grinding mechanism with this system was studied.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.94-101
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• 1998

To form 0.2 .mu.m p$^{+}$-n junctions, BF$_{2}$ ions with the energy of 20keV and the dose of 2*10$^{15}$ cm$^{-2}$ were implanted into the crystalline and preamorphized silicon substrates. Th epreamorphization was performed using 45keV, 3*10$^{14}$ cm$^{-2}$ As or Ge ions. Th efurnace annealing and rapid thermal annealing were empolyed to annihilate the implanted damage and to activate the implanted boron ions.The junction properties were analyzed with the measured values of the junction depth, sheet resistances, residual defects, and leakage currents. The thermal cycle of furnace annela followed by rapid thermal annela shows better characteristics than the annealing sequence of rapid thermal anneal and furnace annela.Among the premorphization species, Ge ion exhibited the better characteristics than the As ion.n.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.421.2-421.2
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• 2014

We report on the growth of ZnO nanorods (NRs) grown on graphite and silicon substrates via an all-solution process and characteristics of their heterojunctions. Structural investigations indicated that morphological and crystalline properties were not significantly different for the ZnO NRs on both substrates. However, optical properties from photoluminescence spectra showed that the ZnO NRs on graphite substrate contained more point defects than that on Si substrate. The ZnO NRs on both substrates showed typical rectification properties exhibiting successful diode formation. The heterojunction between the ZnO NRs and the graphite substrate showed a Schottky diode characteristic and photoresponse under ultraviolet illumination at a small reverse bias of -0.1 V. The results showed that the graphite substrate could be a good candidate for a Schottky contact electrode as well as a conducting substrate for electronic and optoelectronic applications of ZnO NRs.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.71-71
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• 2000

In this paper, the fuzzy system is applied to MCZ Crystal Grower using at industrial field. The existing controller, which is PID controller, has a fixed gain and as a result of it it can not have an adaptive control function against the error or disturbance. Hence, the machine operator should always check the process status and when the error is occurred, the quality and the productivity may be decreased by each personal capability. In order to remove this drawback, a fuzzy control system which is known to be adaptive and flexible is applied to the machine. After applying the fuzzy system, and compared with the existing system, the diameter deviation and the defects were decreased. we proved the possibility of application fuzzy system to single silicon crystal grower.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.229-231
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• 2007

Recently, 3D-electronic packaging by TSV is in interest. TSV(Through Silicon Via) is a interconnection hole on Si-wafer filled with conducting metal such as Copper. In this research, chips with TSV are connected by electroplated Sn bump without PR. Then chips with TSV are put together and stacked by the methode of Reflow soldering. The stacking was successfully done and had no noticeable defects. By eliminating PR process, entire process can be reduced and makes it easier to apply on commercial production.