• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.405-413
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• 2013

In this paper, a high-reliability differential paired 24-bit eFuse OTP memory with program-verify-read mode for PMICs is designed. In the proposed program-verify-read mode, the eFuse OTP memory can do a sensing margin test with a variable pull-up load in consideration of programmed eFuse resistance variation and can output a comparison result through a PFb (pass fail bar) pin by comparing a programmed datum with its read one. It is verified by simulation results that the sensing resistance is lower with $4k{\Omega}$ in case of the designed differential paired eFuse OTP memory than $50k{\Omega}$ in case of its dual-port eFuse OTP memory.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.3
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• pp.51-58
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• 2008

This paper is a study of a prevention of power folding controller's thermal degradation. Power folding technology has been applied for many fields such as side rear vision mirror of vehicles, windshield wiper, antenna, power window. These controllers have been comprised with traditional DC moors, Switching electronic devices, and relays. But this methods have a limitation to overcome such problems of product reliability, endurance, noise margins. Therefore on this paper, to detect the movement of motor, sensing motor brush noise on a load sensing part has been used and controlling a precise RC timing control minimizes the thermal deterioration of motor. And using MOS FETs as a electronic switching device increases life-time and liability of control circuit. After testing such circuit and control method, repetition of operating time, cut-off time, wide operation voltage, power noise margin ware increased over eleven-fold.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.35-35
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• 2009

Capacitorless one transistor dynamic random access memory (1T-DRAM) cells were fabricated on the fully depleted strained-silicon-on-insulator (FD sSOI) and the effects of silicon back interface state on buried oxide (BOX) layer on the memory properties were evaluated. As a result, the fabricated 1T-DRAM cells showed superior electrical characteristics and a large sensing current margin (${\Delta}I_s$) between "1" state and "0" state. The back interface of SOI based capacitorless 1T-DRAM memory cell plays an important role on the memory performance. As the back interface properties were degraded by increase rapid thermal annealing (RTA) process, the performance of 1T-DRAM was also degraded. On the other hand, the properties of back interface and the performance of 1T-DRAM were considerably improved by post RTA annealing process at $450^{\circ}C$ for 30 min in a 2% $H_2/N_2$ ambient.

• Proceedings of the KSRS Conference
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• 2004.10a
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• pp.448-451
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• 2004

MSC (Multi-Spectral Camera) system is an electro-optical camera system which is being developed to be installed on KOMPSAT-2 satellite. High resolution image data from MSC system will be transmitted to the ground-station through x-band antenna called APS (Antenna Pointing System). APS is a directional antenna which will point to the receiving antenna at ground station while the satellite is passing over it. The APS needs to be controlled accurately to provide the reliable communication with big RF link margin. The APS is controlled by ATS (Antenna Tracking Software) which is included in the MSC software. ATS uses the closed loop control algorithm which will use TPF (Tracking Parameter File) as an input for antenna position, and will use two resolve readings from APS as a feedback. ATS has been developed and verified using APS QM (Qualification Model) and all the control parameters for ATS have been tested and verified. Various kinds of maximum, nominal and realistic dynamics for the APS movement have been simulated and verified. In this paper, closed loop servo control algorithm and obtained APS position error from the verification test with APS QM will be presented in detail

• Transactions on Electrical and Electronic Materials
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• v.1 no.1
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• pp.40-44
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• 2000

Metal-ferroelectric-insulator-semoiconductor field effect transistor (MFISFETs) were fabricated using CMOS processes. The Pt/SBT/NO combined layers were etched for forming a conformal gate by using Ti/Cr metal masks and a two step etching method, By the method, we were able to fabricate a small-sized gate with the dimension of $16/4{\mu}textrm{m}$ in the width/length of gate. It has been chosen the non-self aligned source and drain implantation process, We have deposited inter-layer dielectrics(ILD) by low pressure chemical vapor deposition(LPCVD) at $380^{circ}C$ after etching the gate structure and the threshold voltage of p-channel MFISFETs were about 1.0 and -2.1V, respectively. It was also observed that the current difference between the $I_{ON}$(on current) and $I_{OFF}$(off current) that is very important in sensing margin, is more that 100 times in $I_{D}-V_{G}$ hysteresis curve.

• Aerospace Engineering and Technology
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• v.2 no.1
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• pp.108-116
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• 2003

This research presents the design and analysis of PCDU(Power Control & Distribution Unit) of communication satellite. The PCDU of a spacecraft must provide adequate power to each subsystem and payload during mission life, and it also needs high reliability and performance in space environment. A control circuit of the PCDU include bus sensing and filter circuits, error signal amplification circuit, error compensation circuit of SAS(Shunt Assembly Switch) and BPC(Battery Power Converter). The phase margin and DC gain for the designed circuits are analyzed through the frequency response characteristics of the compensated control circuit. And also the transfer function of the battery power converter circuit are discussed at the battery CCCM(Charge Continuous Conduction Mode) and battery C/DCCM(Continuous/Discontinuous Conduction Mode).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.2
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.32-33
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• 2006

As next generation nonvolatile memory, chalcogenide-based phase change memory can substitute for a conventional flash memory from its high performance. Also, fast writing speed, low writing voltage, high sensing margin, low power consumption and repetition reliability over $10^{15}$ cycle shows its possibility. At our laboratory, we invented ${Ge_1}{Se_1}{Te_2}$ material to alternate with conventional ${Ge_2}{Sb_2}{Te_5}$ for improve its ability. We respect the ${Ge_1}{Se_1}{Te_2}$ material can be a solution for high power consumption problem and long time at 'set' performance. A conductivity experiment from variable temperature was performed to see reliability of repetition at read and write performance. Compare with conventional ${Ge_2}{Sb_2}{Te_5}$ material, these two materials are used as complex compound to get the finest parameter.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1426-1427
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• 2006

Chalcogenide based phase-change memory has a high capability and potential for the next generation nonvolatile memory device. Fast writing speed, low writing voltage, high sensing margin, low power consume and long cycle of read/write repeatability are also good advantages of nonvolatile phase-change memory. We have been investigated the new material for the phase-change memory. Its composition is consists of chalcogenide $Ge_{1}Se_{1}Te_2$ material. We made this new material to solve problems of conventional phase-change memory which has disadvantage of high power consume and high writing voltage. In the present work, we are manufactured $Ge_{1}Se_{1}Te_{2}/Ge_{2}Sb_{2}Te_{5}/Ge_{1}Se_{1}Te_{2}$ and $Ge_{2}Sb_{2}Te_{5}/Ge_{1}Se_{1}Te_{2}/Ge_{2}Sb_{2}Te_{5}$ sandwich triple layer structure devices are manufactured to investigate its electrical properties. Through the present work, we are willing to ensure a potential of substitutional method to overcome a crystallization problem on PRAM device.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1329-1330
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• 2007

Phase-change random access memory(PRAM) has many advantages compare with the existing memory. For example, fast programming speed, low programming voltage, high sensing margin, low power consume and long cyclability of read/write. Though it has many advantages, there are some points which must be improved. So, we invented and studied new constitution of $Ge_{1}Se_{1}Te_{2}$ chalcogenide material. Actually, the performance properties have been improved surprisingly. However, crystallization time was as long as ever for amorphization time. In this paper, we studied in order to make set operation time and reset operation voltage reduced. In the present work, by alloying Sb in $Ge_{1}Se_{1}Te_{2}$. we could confirm that improved its set operation time and reset operation voltage. As a result, the method of Sb-alloyed $Ge_{1}Se_{1}Te_{2}$ can be solution to decrease the set operation time and reset operation voltage.