• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.43-47
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• 2004

We have been using Moisture Barrier Bags for dry packing of semiconductor packages to prevent moisture from absorbing during shipping. Moisture barrier bag material is required to be waterproof, vapor proof and offer superior ESD (Electro-static discharge) and EMI shielding. Also, the bag should be formed easily to the shape of products for vacuum packing while providing excellent puncture resistance and offer very low gas ＆ moisture permeation. There are some problems like pinholes and punctured bags after sealing and before the surface mount process. This failure may easily result in package pop corn crack during board mounting. The bags should be developed to meet the requirements of excellent electrical and physical properties by means of optimization of their raw material composition and their thickness. This study investigates the performance of moisture barrier bags by characterization of their mechanical endurance, tensile strength and through thermal analysis. By this study, we arrived at a robust material composition (polyester/Aluminate) for better packing.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.69-73
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• 2008

This article shows that the susceptibility of the device pattern to thermal stress-induced damage has a strong dependence on its proximity to the device comer in semiconductor devices utilizing lead-on-chip (LOC) die attach technique. The result, as explained based on numerical calculation and experiment, indicateds that the stress-driven damage potential of the passivation layer is the highest at the device comer. Thus, the bonding pads, which are very susceptible to passivation damage, should be designed to be located along the central region rather than the peripheral region of the device.

• Journal of the Semiconductor & Display Technology
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• v.5 no.3 s.16
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• pp.5-10
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• 2006

This paper investigates cutting qualities after laser dicing and predicts the problems that can be generated by laser dicing. And through 3 point bending test, die strength is measured and the die strength after laser dicing is compared with the die strength after mechanical sawing. Laser dicing is chiefly considered as an alternative to overcome the defects of mechanical sawing such as chipping on the surface and crack on the back side. Laser micromachining is based on the thermal ablation and evaporation mechanism. As a result of laser dicing experiments, debris on the surface of wafer is observed. To eliminate the debris and protect the surface, an experiment is done using a water soluble coating material and ultrasonic. The consequence is that most of debris is removed. But there are some residues around the cutting line. Unlike mechanical sawing, chipping on the surface and crack on the back side is not observed. The cross section of cutting line by laser dicing is rough as compared with that by mechanical sawing. But micro crack can not be seen. Micro crack reduces die strength. To measure this, 3 point bending test is done. The die strength after laser dicing decreases to a half of the die strength after mechanical sawing. This means that die cracking during package assembly can occur.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.37-42
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• 2011

In this paper, novel carbon nanotube (CNT)-filled Solderable electrically conductive adhesive (ECA) and joining process have been developed. To investigate the bonding characteristics of CNT-filled Solderable ECA, three types of Solderable ECAs with different CNT weight percent (0, 0.1, 1wt%) were formulated. For a joining process, the quad flat package (QFP) chip was used. The QFP chip had a size of $14{\times}14{\times}2.7$ mm and a 1 mm lead pitch. The test board had a Cu daisy-chained pattern with 18 ${\mu}m$ thick. After the bonding process, the bonding characteristics such as morphology of conduction path, electrical resistance and pull strength were measured for each formulated ECAs. As a result, the electrical and mechanical bonding characteristics for a QFP joints using CNT-filled ECA were improved about 10% compared to those of QFP joints using ECA without CNT.

• Journal of the Semiconductor & Display Technology
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• v.15 no.3
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• pp.18-23
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• 2016

QFN (Quad Flat No-leads Package) is one of the SMD (Surface Mount Device). Since there is no lead in QFN, there are many defects on solder. Therefore, we propose an efficient mechanism for QFN solder defect detection at this paper. For this, we employ Convolutional Neural Network (CNN) of the Machine Learning algorithm. QFN solder's color multi-layer images are used to train CNN. Since these images are 3-channel color images, they have a problem with applying to CNN. To solve this problem, we used each 1-channel grayscale image (Red, Green, Blue) that was separated from 3-channel color images. We were able to detect QFN solder defects by using this CNN. In this paper, it is shown that the CNN is superior to the conventional multi-layer neural networks in detecting QFN solder defects. Later, further research is needed to detect other QFN.

• Journal of Welding and Joining
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• v.30 no.3
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• pp.32-37
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• 2012

Lead frame which has a high thermal conductivity and high mechanical strength is one of core technology for ultra-thin electronics such as LED lead frames, memory devices of semiconductors, smart phone, PDA, tablet PC, notebook PC etc. In this paper, we fabricated a Cu/STS/Cu 3-layered clad metal for lead frame packaging materials and characterized the mechanical properties and thermal conductive properties of the clad metal lead frame material. The clad metal lead frame material has a comparable thermal conductivity to typical copper alloy lead frame materials and has a reinforced mechanical tensile strength by 1.6 times to typical pure copper lead frame materials. The thermal conductivity and mechanical tensile strength of the Cu/STS/Cu clad metal are 284.35 W/m K and $52.78kg/mm^2$, respectively.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.12
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• pp.123-128
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• 2021

Liquid dispensing systems are extensively used in various industries such as display, semiconductor, and battery manufacturing. Of the many types of dispensers, drop-on-demand piezoelectric jetting systems are widely used in semiconductor industries because of their ability to dispense minute volumes with high precision. However, due to the problems of nozzle clogging and undesirable dispensing behavior in these dispensers, which often result in device failure, the use of highly viscous fluids is limited. Accordingly, we studied the behaviors of droplet formation based on changes in viscosity. The effects of surface energy and the inner diameters of needle-type nozzles were also studied. Results showed that nozzles with lower surface energies reduced the ejection volume of droplets when a smaller nozzle diameter (0.21 mm in this study) was applied. These results indicate that the hydrophobic treatment of nozzle surfaces and the use of smaller nozzle diameters are critical factors enabling the use of highly viscous fluids in precision dispensing applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.577-584
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• 2015

A photovoltaic (PV) system generates electricity by installing a solar energy array; therefore, the photovoltaic system can be easily exposed to external factors, which include environmental factors such as temperature, humidity, and radiation. These factors-as well as shading, in particular-lead to power degradation. When there is an output loss in the solar cell of a PV module package, the output loss is partly controlled by the bypass diode. As solar cells become highly efficient, the characteristics of series resistance and parallel resistance improve, and the characteristics of reverse voltage change. A bypass diode is connected in parallel to the string that is connected in series to the PV module. Ideally, the bypass diode operates when the voltage is -0.6[V] around. This study examines the bypass diode operating time for different types of crystalline solar cells. It compares the reverse voltage characteristics between the single solar cell and polycrystalline solar cell. Special modules were produced for the experiment. The shading rate of the solar cell in the specially made solar energy module was raised by 5% each time to confirm that the bypass diode was operating. The operation of the bypass diode is affected not only by the reverse voltage but also by the forward bias. This tendency was verified as the number of strings increased.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.10
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• pp.1011-1019
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• 2015

Insulated-gate bipolar transistors (IGBTs) are the predominantly used power semiconductors for high-current applications, and are used in trains, airplanes, electrical, and hybrid vehicles. IGBT power modules generate a considerable amount of heat from the dissipation of electric power. This heat generation causes several reliability problems and deteriorates the performances of the IGBT devices. Therefore, thermal management is critical for IGBT modules. In particular, realizing a proper thermal design for which the device temperature does not exceed a specified limit has been a key factor in developing IGBT modules. In this study, we investigate the thermal behavior of the 1200 A, 3.3 kV IGBT module package using finite-element numerical simulation. In order to minimize the temperature of IGBT devices, we analyze the effects of various packaging materials and different thickness values on the thermal characteristics of IGBT modules, and we also perform a design-of-experiment (DOE) optimization