• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.1-8
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• 2006

In this paper, reliability (HCI, NBTI) and device performance of nano-scale CMOSFETs with different channel stress were investigated. It was shown that NMOS and PMOS performances were improved by tensile and compressive stress, respectively, as well known. It is shown that improved device performance is attributed to the increased mobility of electrons or holes in the channel region. However, reliability characteristics showed different dependence on the channel stress. Both of NMOS and PMOS showed improved hot carrier lifetime for compressive channel stress. NBTI of PMOS also showed improvement for compressive stress. It is shown that $N_{it}$ generation at the interface of $Si/SiO_2$ has a great effect on the reliability. It is also shown that generation of positive fixed charge has an effect in the NBTI. Therefore, reliability as well as device performance should be considered in developing strained-silicon MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.370-377
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• 2017

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.25-28
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• 2001

Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. Without applying the conventional complex reverse moat process, CMP(Chemical Mechanical Polishing) has established the Process simplification. However, STI-CMP process have various defects such as nitride residue, torn oxide defect, damage of silicon active region, etc. To solve this problem, in this paper, we discussed to determine the control limit of process, which can entirely remove oxide on nitride from the moat area of high density as reducing the damage of moat area and minimizing dishing effect in the large field area. We, also, evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.3
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• pp.43-49
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• 2013

Recently harmonics flowing into power system is increasing as the usage of semiconductor equipments and switching mode power equipments are increasing. Harmonics cause problems such as heat increasing and reduction in capacity of transformers, especially the harmonics flowing into a distribution transformer can lead to the lifetime reduction of transformer. In this paper, we are about to develop a device that can monitor harmonics in real-time as it is affixed to a distribution transformer. Unlike the existing expensive harmonic analysis device, a new harmonic analysis algorithm is proposed in order to implement low-cost equipment. The real-time harmonic analysis algorithm proposed in this paper allows implementation on low performance microcontrollers, thus it can monitor the harmonic in real-time as it is individually affixed to the transformer. Therefore, it would improve the reliability of the transformer and stable power system operation would be possible as it can prevent the transformer accidents in advance.

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.3-3
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• 1995

Plastic IC encapsulation utilizing lead on chip(LOC) die attach technique allows higher device density per unit package area, and faster current speed and easter leadframe design. Nevertheless, since the top surface of the chip is directly attached to the area of the leadframe with a double-sided adhesive tape in the LOC package, it tends to be easily damaged by the leadframe, leading to limitation in its utilization. In this work, it is detailed how the damage of the chip surface occurs, and it is influenced and improved by the LOC construct.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.1
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• pp.327-332
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• 2021

At the package level, semiconductor reliability inspections involves mounting a semiconductor chip package on a test socket. The form of the test socket is basically determined by the form of the chip package. It also acts as a medium to connect with test equipment through mechanical contact of the leads and socket leads in the chip package, and it minimizes signal loss in a signal transmission process so that an inspection signal can be delivered well to the semiconductor. In this study, a technique was applied to examine the interdependence of adjacent electrical transfer routes and the structure of adjacent electrical transfer paths. The goal was to enable short-circuit testing of fewer than 100 silicon test sockets through a single interface for life tests and precision measurements. The test results of the developed device show a test precision of 99% or more and a simultaneous test speed characteristic of 0.66 sec or less.

• Journal of the Semiconductor & Display Technology
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• v.8 no.4
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• pp.49-52
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• 2009

We have investigated the effect of the surface roughness of TCO substrate on the characteristics of OLED (organic light emitting diodes) devices. In order to control the surface roughness of ITO thin films, we have processed photolithography and reactive ion etching. The micro-size patterned mask was used, and the etching depth was controlled by changing etching time. The surface morphology of the ITO thin film was observed by FESEM and atomic force microscopy (AFM). And then, organic materials and cathode electrode were sequentially deposited on the ITO thin films. Device structure was ITO/$\alpha$-NPD/DPVB/Alq3/LiF/Al. The DPVB was used as a blue emitting material. The electrical characteristics such as current density vs. voltage and luminescence vs. voltage of OLED devices were measured by using spectrometer (minolta CS-1000A). The current vs. voltage and luminance vs. voltage characteristics were systematically degraded with increasing surface roughness. Furthermore, the retention test clearly presented that the reliability of OLED devices was directly influenced with the surface roughness, which could be interpreted in terms of the concentration of the electric field on the weak and thin organic layers caused by the poor step coverage.

• Journal of Power System Engineering
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• v.4 no.1
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• pp.45-50
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• 2000

Circuit breakers have traditionally employed mechanical methods to interrupt excessive currents. According to power semiconductor technology advances in power electronic device, some mechanical breakers are replaced with solid state equivalents. Advantages of the contactors using semiconductor devices include faster fault interrupting, fault current limiting, no arc to contain or extinguish and intelligent power control, and high reliability. This paper describes the design of a static $100{\pm}10%V$ and 0 to 50A DC self-protected contactor with 85A "magnetic tripping" and 100A interruption current at $2.2A/{\mu}s$ short circuit of load condition using a new power device the HARRIS MCT (600V-75A). The self-protection circuit of this system is designed by the classical ZnO varistor for energy absorption and turn-off snubber circuit ("C" or "RCD") of the MCT.

• Journal of the Semiconductor & Display Technology
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• v.9 no.4
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• pp.25-29
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• 2010

We have investigated the effect of surface roughness of TCO substrate on the characteristics of OLED (organic light emitting diodes) devices. In order to control the surface roughness of AZO thin films, we have processed photo-lithography and reactive ion etching. The micro-size patterned mask was used, and the etching depth was controlled by changing etching time. The surface morphology of the AZO thin film was observed by FESEM and atomic force microscopy (AFM). And then, organic materials and cathode electrode were sequentially deposited on the AZO thin films. Device structure was AZO/${\alpha}$-NPD/DPVB/$Alq_3$/LiF/Al. The DPVB was used as a blue emitting material. The electrical characteristics such as current density vs. voltage and luminescence vs. voltage of OLED devices were measured by using spectrometer. The current vs. voltage and luminance vs. voltage characteristics were systematically degraded with increasing surface roughness. Furthermore, the retention test clearly presented that the reliability of OLED devices was directly influenced with the surface roughness, which could be interpreted in terms of the concentration of the electric field on the weak and thin organic layers caused by the poor step coverage.