JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Simple Static Noise Margin Model of MOS CML Gate in CMOS Processes

  • Jeong, Hocheol (School of Electrical Engineering and Computer Sciences, Gwangju Institute of Science and Technology (GIST)) ;
  • Kang, Jaehyun (School of Electrical Engineering and Computer Sciences, Gwangju Institute of Science and Technology (GIST)) ;
  • Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Minjae (School of Electrical Engineering and Computer Sciences, Gwangju Institute of Science and Technology (GIST))
  • Received : 2016.06.13
  • Accepted : 2017.03.23
  • Published : 2017.06.30
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Abstract

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.

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References

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