• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.4
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• pp.27-37
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• 2009

This paper is about the architectures of an extensible and scalable home automation system which is based on instant messaging. The extensibility is the most important feature of the system because there are very diverse appliances at home and they can be added or replaced with other products frequently. For the extensibility, we propose façade architecture for communication, distributed agent architecture for the system, layered architecture for agents, and bridge architecture for wrapping existing facilities. Using these architectures, we reduce the system complexity and get the extensibility to add new products with least cost. Furthermore, we also introduce our prototype system and show that it is extensible.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.610-613
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• 2002

To improve quality of service(QoS) in the current Internet, various QoS providing mechanisms such as RSVP, DiffServ have been proposed. In this paper we propose a more simple but more scalable mechanism which can guarantee end-to-end QoS. The proposed mechanism can provide scalability by minimizing the state information which is needed by router to reserve network resources. Using sender-initiated & soft-state resource reservation, a router does not need to keep the backward data path like RSVP. In this paper we illustrate the proposed resource reservation mechanism with network topology and signaling.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7C
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• pp.641-652
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• 2002

We introduce a new ultra-large capacity time- and wavelength-division hybrid optical switching system, called ESCIMONET(Easily SCalable Interconnected Multiwavelength Optical NETwork). We describe its architecture, principle of operation, and performance characteristics. ESCIMONET is very effective system in terms of its handling capacity versus number of wavelength needed. It can handle n$^3$number of channels using only n number of different wavelengths. The insertion loss of the whole system is less than conventional optical switching system so that the number of optical amplifiers in the system can be minimized. We analyzed the performance of the system by investigation the characteristics of the buffer used in the system such as throughput and average waiting time of the signal in a buffer.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.9
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• pp.503-513
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• 2002

Since CC-NUMA architecture has to access remote memory, the interconnection network determines the performance of the CC-NUMA system. Bus which has been used as a popular interconnection network has many limits in a large-scale system because of the limited physical scalability and bandwidth. The dual ring interconnection network, composed of high-speed point-to-point links, is made to resolve the defects of the bus for the large-scale system. However, it also has a problem, in that the response latency is rapidly increased when many nodes are attached to the snooping based CC-NUMA system with the dual ring. In this paper, we propose a ring architecture with repeater nodes in order to overcome the problem of the dual ring on a snooping based CC-NUMA system, and design a repeater node adapted to this architecture. We will also analyze the effects of proposed architecture on the system performance and the response latency by using a probability-driven simulator.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.4
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• pp.242-250
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• 2007

Wireless sensor networks are subject to highly heterogeneous system requirements in terms of their functionality and performance due to their broad application areas. Though the heterogeneity hinders the opportunity of developing a single universal platform for sensor networks, efforts to provide uniform, inter-operable and scalable ones for sensor networks are still essential for the growth of the industry as well as their technological advance. As a part of our work to develop such a robust platform, this paper presents the software architecture for sensor nodes with focus on our sensor node operating system and its configuration methodology. Addressing principle issues in its design space which includes programming, execution, task scheduling and software layer models, our architecture is highly reconfigurable with respect to system resources and functional requirements and also highly efficient in supporting multi-threading under small system resources.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.415-422
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• 2013

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.376-379
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• 1999

The wavelet transform chip is implemented with Daubechies' 4 tap filter. It works at 20MHz in Field Programmable Gate array (FPGA) implementation of Quadrature Mirror Filter(QMF) Lattice Structure. In this paper, the structure contains taro-channel quadrature mirror filter, data format converter(DFC), delay control unit(DCU), and three 20$\times$8 bits real multiplier. The structures for the DFC and DCU need to he regular and scalable, require minimum number of regular, and thereby lead to an efficient and scalable architecture for the Discrete Wavelet Transform(DWT). These results present the possibility that it can be used in Digital Signal Processing(DSP) application faster than Fourier transform at small area with lour cost.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• Journal of Broadcast Engineering
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• v.20 no.5
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• pp.756-769
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• 2015

In this paper, we propose a scalable coding method for high dynamic range (HDR) and standard dynamic range (SDR) videos based on Scalable High Efficiency Video Coding (SHVC). The proposed method has multi-layer coding architecture that consists of base layer for SDR videos and enhancement layer for HDR videos to support the backward compatibility with legacy codec and display devices. Also, to improve coding efficiency of enhancement layers, a global inverse tone mapping is applied to the reconstructed SDR video and the compensated frames are referred for coding of the enhancement layer. The proposed method is found to achieve BD-Rate gain of 43.0% on average (maximum 76.3%) for the enhancement layer and 15.7% on average (maximum 31%) for dual-layer against the SHM 7.0 reference software.

• International Journal of Internet, Broadcasting and Communication
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• v.8 no.1
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• pp.33-41
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• 2016

Big data management is becoming an increasingly important issue in both industry and academia of information science community today. One of the important categories of big data generated from software systems is log data. Log data is generally used for better services in various service providers and can also be used to improve system reliability. In this paper, we propose a novel big data management architecture specialized for log data. The proposed architecture provides a scalable log management system that consists of client and server side modules for efficient handling of log data. To support large and simultaneous log data from multiple clients, we adopt the Hadoop infrastructure in the server-side file system for storing and managing log data efficiently. We implement the proposed architecture to support various client environments and validate the efficiency through measurement studies. The results show that the proposed architecture performs better than the existing logging architecture by 42.8% on average. All components of the proposed architecture are implemented based on open source software and the developed prototypes are now publicly available.