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Electrical Budgets Measurements in PCI Express System (PCI Express 시스템의 전기 파라미터 측정)

  • Gwon, Won-Ok;Kim, Seong-Un
    • Electronics and Telecommunications Trends
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    • v.22 no.4 s.106
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    • pp.133-143
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    • 2007
  • PCI Express는 고속 차동신호를 사용한 점대점(point-to-point) 프로토콜로 신호무결성(signal-integrity) 측정을 위해 기존의 병렬버스신호와 다른 파라미터(parameter)들이 사용되고 있다. PCI Express 시스템에서 중요한 전기 파라미터는 loss와 jitter이며 eye diagram을 통해서 분석이 가능하다. 본 고는 PCI Express 송수신 버퍼의 전기 규격과 애드인카드(add-in card) 시스템의 전기적 여유(budgets)의 의미와 분석을 다룬다. 또한 실제적인 PCI Express 시스템에서 전기 파라미터들을 측정하고 분석, 디버깅의 방법을 다룬다.

A central limit theorem for sojourn time of strongly dependent 2-dimensional gaussian process

  • Jeon, Tae-Il
    • Journal of the Korean Mathematical Society
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    • v.32 no.4
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    • pp.725-737
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    • 1995
  • Let $X_t = (X_t^(1), X_t^(2))', t \geqslant 0$, be a real stationary 2-dimensional Gaussian process with $EX_t^(1) = EX_t^(2) = 0$ and $$ EX_0 X'_t = (_{\rho(t) r(t)}^{r(t) \rho(t)}), $$ where $r(t) \sim $\mid$t$\mid$^-\alpha, 0 < \alpha < 1/2, \rho(t) = o(r(t)) as t \to \infty, r(0) = 1, and \rho(0) = \rho (0 \leqslant \rho < 1)$. For $t > 0, u > 0, and \upsilon > 0, let L_t (u, \upsilon)$ be the time spent by $X_s, 0 \leqslant s \leqslant t$, above the level $(u, \upsilon)$.

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Geometric Interpretation on Chebyshev Type Inequalities

  • Lee, Kee-Won;Kim, Yoon-Tae
    • Communications for Statistical Applications and Methods
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    • v.6 no.1
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    • pp.261-266
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    • 1999
  • We present a geometric interpretation of Chebyshev type inequalities. This uses a simple diagram which illustrates the functional bound for the indicator function of the event whose probability we want to assess. We also give a geometric interpretation of the inequalities in terms of volume in a Euclidean space of appropriate dimension. Markov's inequality and Chebyshev's inequality are treated in more detail.

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CMOS Current Sum/Subtract Circuit

  • Parnklang, Jirawath;Manasaprom, Ampual
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.108.6-108
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    • 2001
  • The basic circuit block diagram of CMOS current mode sum and subtract circuit is present in this paper. The purpose circuit consists of the invert current circuit and the basic current mirror. The outputs of the circuit are the summing of the both input current [lx+ly] and also the subtract of the both input current [lx+(-ly)]. The SPICE simulation results of the electrical characteristics with level 7 (BSIM3 model version 3.1) MOSFET transistor model of the circuit such as the input dynamic range, the frequency response and some system application have been shown and analyzed.

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InP JFET Devices for High Speed Switching Application (광대역 교환을 위한 InP JFET소자)

  • 지윤규;김성준;정종민
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.5
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    • pp.370-374
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    • 1991
  • A high performance fully ion-implanted InP JFET was characterized for high speed switching elements. The switch has an insertion loss of 5.5dB with 31.6dB isolation at 1GHz. This device can effectively swithc a byte-multiplexed 2Gb/s signal and an eye-diagram taken at 2Gb/s shows an error-free eye pattern. Therefore, this device can be used as a switching element for high transmission data rate for monolithic integration of optoelectronic circuit in the long-wavelength region.

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A Methodology of Extended Object-Oriented Software on UML (UML을 기반으로 한 확장된 객체지향 소프트웨어 개발 방법론)

  • 최금희;허계범;최영근
    • Proceedings of the Korean Information Science Society Conference
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    • 1999.10a
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    • pp.463-465
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    • 1999
  • Objectory Process를 바탕으로 한 Rose는 실 프로젝트의 개발을 위한 단계에 대한 구체적인 절차제시 및 세부적인 지침의 부족으로 실제 업무 개발 시 혼란을 초래할 수 있다. 본 논문에서는 Objectory Process를 확장하여 개발자를 위한 객체지향 소프트웨어 개발 방법론을 제시한다. 그리고, UML Diagram과 세부적인 명세서 작성방법 및 산출물을 명시하고, 이와 같은 정보들 저장 및 검색을 관리 할 수 있는 효율적인 객체지향 소프트웨어 개발 방법론을 제시한다.

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A Characterization of Nonnil-Projective Modules

  • Hwankoo Kim;Najib Mahdou;El Houssaine Oubouhou
    • Kyungpook Mathematical Journal
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    • v.64 no.1
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    • pp.1-14
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    • 2024
  • Recently, Zhao, Wang, and Pu introduced and studied new concepts of nonnil-commutative diagrams and nonnil-projective modules. They proved that an R-module that is nonnil-isomorphic to a projective module is nonnil-projective, and they proposed the following problem: Is every nonnil-projective module nonnil-isomorphic to some projective module? In this paper, we delve into some new properties of nonnil-commutative diagrams and answer this problem in the affirmative.

Forming Limit Diagram of DP590 considering the Strain Rate (변형률속도를 고려한 DP590의 성형한계도)

  • Kim, Seok-Bong;Ahn, Kwang-Hyun;Ha, Ji-Woong;Lee, Chang-Soo;Huh, Hoon;Bok, Hyun-Ho;Moon, Man-Been
    • Transactions of the Korean Society of Automotive Engineers
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    • v.18 no.1
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    • pp.127-130
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    • 2010
  • This paper deals with the formability of DP590 steel considering the strain rate. The strain hardening coefficient, elongation and r-value were obtained from the static and dynamic tensile test. As strain rate increases from static to 100/s, the strain hardening coefficient and the uniform elongation decrease and the elongation at fracture and r-value decrease to 0.1/s and increase again to 100/s. The high speed forming limit tests with hemi-spherical punch were carried out using the high speed crash testing machine and high speed forming jig. The high speed forming limit of DP590(order of $10^2$/s) decreases compared to the static forming limit(order of $10^{-3}$/s) and the forming limit band in high speed forming test is narrower than that in the static forming test. This tendency may be due to the development of brittleness with increase of stain rate.

Test Generation for Partial Scanned Sequential Circuits Based on Boolean Function Manipulation (논리함수처리에 의한 부분스캔순차회로의 테스트생성)

  • Choi, Ho-Yong
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.3
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    • pp.572-580
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    • 1996
  • This paper describes a test generation method for sequential circuits which improves the application limits of the IPMT method by applying the partial scan design to the IPMT method. To solve the problem that the IPMT method requires enormous computation time in image computation, and generates test patterns after the partialscan design is introduced to reduce test complexity. Scan flip-flops are selected for the partial scan design according to the node size of the state functions of a sequential circuit in their binary decision diagram representations. Experimental results on ISCAS'95 benchmark circuits show that a test generator based on our method has achieved 100% fault coverage by use of either 20% scan FFs for s344, s349, and s420 or 80% scan FFs for sl423. However, test gener-ators based on the previous IPM method have not achieved 100% fault coverage for those circuits.

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INFRARED AND HARD X-RAY DIAGNOSTICS OF AGN IDENTIFICATION FROM THE AKARI AND SWIFT/BAT ALL-SKY SURVEYS

  • Matsuta, K.;Gandhi, P.;Dotani, T.;Nakagawa, T.;Isobe, N.;Ueda, Y.;Ichikawa, K.;Terashima, Y.;Oyabu, S.;Yamamura, I.;Stawarz, L.
    • Publications of The Korean Astronomical Society
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    • v.27 no.4
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    • pp.285-286
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    • 2012
  • We combine data from two all-sky surveys, the Swift/Burst Alert Telescope 22 Month Source Catalog and the AKARI Point Source Catalogue, in order to study the connection between the hard X-ray (> 10 keV) and infrared (IR) properties of local active galactic nuclei (AGN). We find two photometric diagnostics are useful for source classification: one is the X-ray luminosity vs. IR color diagram, in which type 1 radio-loud AGN are well isolated from other AGN. The second one uses the X-ray vs. IR color-color diagram as a redshift-independent indicator for identifying Compton-thick (CT) AGN. Importantly, CT AGN and starburst galaxies in composite systems can also be separated in this plane based upon their hard X-ray fluxes and dust temperatures. This diagram may be useful as a new indicator to classify objects in new surveys such as with WISE and NuSTAR.