• Title/Summary/Keyword: reset time

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Effect of Address Discharge Characteristics by Selective Reset Method in AC Plasma Display Panel (교류형 플라즈마 디스플레이에서 선택적 초기화 방법에 의한 기입 방전 특성의 영향)

  • Cho, Byung-Gwon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.12
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    • pp.1004-1008
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    • 2012
  • The effect of address discharge characteristics by selective reset method is investigated to prevent the weakness of address discharge in the middle of a TV-field without increase of the black luminance. To reduce black luminance in AC PDP usually, the first subfield during one TV frame adopted the conventional rising ramp-reset waveform, whereas the other subfields adopted the subsidiary reset waveform without rising ramp type. As the wall charge for the address discharge was accumulated by only the rising ramp waveform during the first reset period, the wall charge on three electrodes was disappeared as time passed and the address discharge would be weakened in the rear subfields. To prevent a reduction of the address discharge characteristics without decrease the black luminance, the modified rising ramp reset waveform was adopted only in the sixth subfield. As a result, a modified driving method could improve the address discharge characteristics compared with selective reset driving scheme with almost the same black luminance.

RMSP (Ramp biased Multiple Short Pulses) reset method for AC PDP

  • Yang, Jin-Ho;Kim, Jae-Seong;Jung, Jae-Chul;Whang, Ki-Woong;Chung, Woo-Joon
    • 한국정보디스플레이학회:학술대회논문집
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    • 2003.07a
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    • pp.325-328
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    • 2003
  • We have proposed a new reset discharge method for AC PDP, which is composed of fast Ramp biased Multiple Short Pulses (RMSP). By using this method, we achieved stable reset discharges with reduced reset time. At the same time, it resulted in lower background luminance as well as stable and higher address margin using the tail effect.

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A Study of Negative Waveform in ac PDP during Reset and Address Periods (ac PDP에서의 Reset과 Address 구간에서 Negative Waveform특성에 관한 연구)

  • Eom, Cheol-Hwan;Kang, Jung-Won
    • Journal of the Semiconductor & Display Technology
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    • v.8 no.1
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    • pp.27-31
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    • 2009
  • A characteristic of new waveform, called a negative waveform, was studied during reset and address periods. IR distribution, black luminance and time delay were measured to compare the negative waveform with the conventional positive waveform. Based on the analysis of IR measurement, the negative waveform could accumulate more wall charges than the positive waveform. Also the black luminance of negative waveform was lower than that of positive waveform under the same bias and ramp-slope conditions. During address period, the discharge time lag was measured. The negative waveform was showed 0.25 us faster formative time lag and 0.1 us faster average time lag than those of positive waveform.

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A New Reset Waveform for Reducing Reset Period in AC-PDP (교류형 플라즈마 디스플레이의 리셋구간 단축을 위한 새로운 리셋 파형)

  • Kim, Gun-Su;Choi, Hoon-Young;Kim, Son-Ic;Kim, Jun-Hyoung;Jung, Hai-Young;Min, Byoung-Kuk;Lee, Seok-Hyun
    • Proceedings of the KIEE Conference
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    • 2002.07c
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    • pp.1636-1639
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    • 2002
  • We proposed the new reset waveform for reducing reset period. The square pulse is applied to the address electrode when the ramp pulse increases before a discharge occurs between sustain electrodes. If the discharge occurs between address electrode and X electrode, the wall charge is reversely accumulated between sustain electrodes compared with the applying voltage before the discharge occurs between sustain electrodes. So the next discharge more weakly occurs between sustain electrodes. If the more weak discharge is obtained, it can make the low background luminance and the high contrast ratio and reduce ramp up time in the ramp reset waveform.

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New Selective Reset Waveform for a Large-Sustain-Gap Structure in AC PDPs (AC PDP의 장방전 구조의 구동을 위한 새로운 셀렉티브 리셋파형)

  • Song, Tae-Yong;Kim, Dong-Hun;Kim, Won-Jae;Lee, Seok-Hyun
    • Proceedings of the KIEE Conference
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    • 2007.07a
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    • pp.1391-1392
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    • 2007
  • A selective reset waveform which can improve the dark room contrast ratio in a large sustain gap structure is suggested in this paper. When conventional selective reset discharge is performed, frequent unexpected misfiring happens because of high Vxb and much quantity of negative wall charge formed on Y electrode during final sustain period. The misfiring between sustain electrode and address electrode can be removed by lowering Vxb value and the misfiring between address electrode and scan electrode can be prevented by applying last sustain pulse of 40us and rectangular pulse of Vscan on Y electrode. When the selective reset waveform has one time reset per 8 subfields, black luminance of 1.55 cd/m2 can be obtained without any misfiring.

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Relationship between Image Retention and Time Lag in an AC PDP

  • Do, Yun-Seon;Jang, Cheol;Choi, Kyung-Cheol
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.613-616
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    • 2007
  • Characteristics of dark image retention and address discharge time lag were investigated simultaneously. It was found that reset waveforms with low black luminance did not guarantee lower image retention. Improved address discharge time lag due to modified reset waveforms similarly did not show improved image retention. The address discharge time lag and the image retention are in a trade-off relation.

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Online Learning Control for Network-induced Time Delay Systems using Reset Control and Probabilistic Prediction Method (네트워크 기반 시간지연 시스템을 위한 리세트 제어 및 확률론적 예측기법을 이용한 온라인 학습제어시스템)

  • Cho, Hyun-Cheol;Sim, Kwang-Yeul;Lee, Kwon-Soon
    • Journal of Institute of Control, Robotics and Systems
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    • v.15 no.9
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    • pp.929-938
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    • 2009
  • This paper presents a novel control methodology for communication network based nonlinear systems with time delay nature. We construct a nominal nonlinear control law for representing a linear model and a reset control system which is aimed for corrective control strategy to compensate system error due to uncertain time delay through wireless communication network. Next, online neural control approach is proposed for overcoming nonstationary statistical nature in the network topology. Additionally, DBN (Dynamic Bayesian Network) technique is accomplished for modeling of its dynamics in terms of casuality, which is then utilized for estimating prediction of system output. We evaluate superiority and reliability of the proposed control approach through numerical simulation example in which a nonlinear inverted pendulum model is employed as a networked control system.

The Reduction of Address Discharge Delay Time Using a New Driving Method (새로운 구동방식을 이용한 어드레스 방전 지연시간의 감소)

  • Song, Keun-Young;Kim, Gun-Su;Seo, Jeong-Hyun;Lee, Seok-Hyun
    • Proceedings of the KIEE Conference
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    • 2004.11a
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    • pp.123-125
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    • 2004
  • In order to achieve high efficiency and low cost, new high-speed addressing method is suggested. This can be achieved by reducing the address discharge delay time through the priming effect. This paper suggests a new ADR (Address During Reset) driving method which provides priming particles by using a separated driving method without adding auxiliary electrode or auxiliary discharge. The experimental results show an approximately loons reduction in the formative delay time of address discharge and a reduction in jitter of over 200ns. Also, due to enough time being available for reset, there was a reduction in light emitted during reset of about 29% which improved the dark contrast ratio considerably.

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Low Cost Driving System for Plasma Display Panels by Eliminating Path Switches and Merging Power Switches

  • Lee, Dong-Myung;Hyun, Dong-Seok
    • Journal of Power Electronics
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    • v.7 no.4
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    • pp.278-285
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    • 2007
  • Recently, plasma display panels (PDP) have become the most promising candidate in the market for large screen size flat panel displays. PDPs have many merits such as a fast display response time and wide viewing angle. However, there are still concerns about high cost because they require complex driving circuits composed of high power switching devices to generate various voltage waveforms for three operational modes of reset, scan, and sustain. Conventional PDP driving circuits use path switches for voltage separation and a scan switch to offer a scan voltage for reset and scan operations, respectively. In addition, there exist reset switches to initialize PDPs by regulating the wall charge conditions with ramp shaped pulses, which means the necessity of specific power devices for the reset operation. Because power for the plasma discharge accompanied by a large current is transferred to a panel via path switches, high power rating switches are used for path switches. Therefore, this paper proposes a novel low-cost PDP driving scheme achieved by not only eliminating path switches but also merging the function of reset switches into other switches used for sustain or scan operations. The simulated voltage waveforms of the proposed topology and experimental results implemented in a 42-inch panel to demonstrate the validity of using a new gate driver that merges the functions of power switches are presented.

A Study on the Characteristics of Priming Discharge in the PDPs (PDP의 프라이밍 방전특성에 관한 연구)

  • 손현성;채승엽;염정덕
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2002.11a
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    • pp.29-33
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    • 2002
  • Period which does an electric condition of panel in reset in the driving method of PDP is reset period. This research experimentally analyzed the priming discharge characteristic of reset period. The amount of wall charge and the accumulation time accumulated by priming discharge are unrelated to width of priming pulse. And, self-erase discharge has the relation in the amount of wall charge by priming discharge. Then, it relates also to space charge generated by priming discharge. Moreover, space charge which helps self-erase discharge exists to about 22$mutextrm{s}$ after generating priming discharge. And, it is suitable within 12$mutextrm{s}$ of priming pulse width for efficient reset.

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