• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.429-432
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• 1998

The impact of hot carrier induced gate leakage current on the refresh time of memory devices has been examined. The maximum allowable supply voltage for cell transistor has been determined form the degradation of the refresh time. The desing guideline for cell capacitors and refresh circuits has been suggested.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.4
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• pp.23-30
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• 2004

In MPEG-4 video, Motion Adaptive Intra Refresh (MAIR) encodes a motion area macroblock in intra mode, thereby preventing the error propagation. Motion area is selected by difference of between current macroblock and previous macroblock. An effective implementation of the AIR is to reduce the maximum refresh time and estimate the error prone macroblock. However in the case or the MAIR, unnecessary macroblock can be encoded in intra mode. in this paper, a bitrate AIR is proposed that reduces the maximum refresh time by estimating the error prone macroblock more efficiently.

• Journal of Korea Multimedia Society
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• v.7 no.12
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• pp.1754-1764
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• 2004

Lately mobile handheld devices such as Personal Digital Assistant (PDA) and cellular phones are getting more popular for personal web surfing. However, today most mobile handheld devices have relatively poor web browsing capability due to their low performance so their users have to suffer longer communication latency than those of desktop Personal Computers (PCs). In this paper, we propose an effective pre-refresh mechanism for embedded web browser of mobile handheld devices to reduce this problem. The proposed mechanism uses the idle time to pre-refresh the expired web objects in an embedded web browser's cache memory. It increases the utilization of Central Processing Unit (CPU) power and network bandwidth during the idle time and consequently reduces the client's latency and web browsing cost. An experiment was done using a simulator designed by us to evaluate the efficacy of the proposed mechanism. The experiment result demonstrates that it has a good performance to make web surfing faster.

• ETRI Journal
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• v.26 no.6
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• pp.583-588
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• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.2
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• pp.117-122
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• 2016

Optimizing the number of ad clicks is a large-scale learning problem that is central to the multi-billion dollar mobile advertising industry. There are currently several optimization methods used, including ad mediation and ad positioning. This paper proposes a new method to optimize mobile advertising by using the ad refresh interval. A new metric, which can measure and compare mobile advertising performance, takes into account time limitations. The results achieved from this optimization study could maximize revenue for mobile advertisers and publishers. This research has high applicability. It also lays out a solid background for future research in this promising area.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.232-234
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• 1996

The self-refresh mode was introduced as method to reduce power dissipation in DRAM. Because the data retention time of DRAM cell decreases as the ambient temperature rises, the internal period in self-refresh mode must be limited by retention capability at the highest temperature in DRAM specification. Because of this, at room temperature($25^{\circ}C$) unnecessary power dissipation happens, If the period of self-refresh could be modulated as temperature, it is possible to reduce the self-refresh current. In this paper, new temperature detector circuit is suggested as this purpose.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.179-185
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• 2020

DRAM is a major component of the main memory system. As the operating system evolves and application complexity and capacity increases, the capacity and speed of DRAM are also increasing. DRAM should perform a refresh action of periodically reading and then re-storing stored values, and the accompanying performance and power/energy overhead embodies characteristics that worsen as capacity increases. This study proposes an energy efficiency improvement technique that efficiently stores the rows that need to be refreshed within 64ms and 128ms using the bloom filter for cells with the lowest retention time of electrons. The results of the experiment showed that the proposed technique resulted in an average 5.5% performance improvement, 76.4% reduction in average refresh energy, and 10.3% reduction in average EDP.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.126-129
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• 2006

We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

• Journal of the Korean Vacuum Society
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• v.3 no.1
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• pp.71-76
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• 1994

The electrical characteristics of the capacitor dielectric films of amorphous silicon-nit-ride-oxide(ANO) structures are compared with the capacitor dielectric films of oxide-nitride-oxide (ONO) structrues The electrical characteristics of ONO and ANO films were evaluated by high frequency(1 MHz) C-V high frequency C-V after constant voltage stree I-V TDDB and refresh time measurements. ANO films shows good electrical characteristics such as higher total charge to breakdown storage capacitance and longer refresh time than ONO films. Also it makes little difference that leakage current and flat band voltage shyift(ΔVfb)of ANO ana ONO films.

• Journal of the Korea Society for Simulation
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• v.9 no.4
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• pp.51-58
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. The novel junction process scheme in sub-micron DRAM cell with STI(Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this' paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ${\Delta}Rp$ (projected standard deviation) increase using buffered N-implantation with tilt and 4X(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is Intentionally caused by ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and Nd/Na ratio. We used MEDICI Simulator to confirm the junction device characteristics. And measured the refresh time using the ADVAN Probe tester.