• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제16권2호
• /
• pp.658-675
• /
• 2022

This paper presents a fast-simplified successive cancellation (SC) flipping (Fast-SSC-Flip) decoding algorithm for polar code. Firstly, by researching the probability distribution of the number of error bits in a node caused by channel noise in simplified-SC (SSC) decoder, a measurement criterion of node reliability is proposed. Under the guidance of the criterion, the most unreliable nodes are firstly located, then the unreliable bits are selected for flipping, so as to realize Fast-SSC-Flip decoding algorithm based on node reliability (NR-Fast-SSC-Flip). Secondly, we extended the proposed NR-Fast-SSC-Flip to multiple node (NR-Fast-SSC-Flip-ω) by considering dynamic update to measure node reliability, where ω is the order of flip-nodes set. The extended algorithm can correct the error bits in multiple nodes, and get good performance at medium and high signal-to-noise (SNR) region. Simulation results show that the proposed NR-Fast-SSC-Flip decoder can obtain 0.27dB and 0.17dB gains, respectively, compared with the traditional Fast-SSC-Flip [14] and the newly proposed two-bit-flipping Fast-SSC (Fast-SSC-2Flip-E2) [18] under the same conditions. Compared with the newly proposed partitioned Fast-SSC-Flip (PA-Fast-SSC-Flip) (s=4) [18], the proposed NR-Fast-SSC-Flip-ω (ω=2) decoder can obtain about 0.21dB gain, and the FER performance exceeds the cyclic-redundancy-check (CRC) aided SC-list (CRC-SCL) decoder (L=4).

• 한국HCI학회:학술대회논문집
• /
• 한국HCI학회 2006년도 학술대회 1부
• /
• pp.931-936
• /
• 2006

This paper presents different issues of the real-time compression algorithms without compromising the video quality in the distributed environment. The theme of this research is to manage the critical processing stages (speed, information lost, redundancy, distortion) having better encoded ratio, without the fluctuation of quantization scale by using IP configuration. In this paper, different techniques such as distortion measure with searching method cover the block phenomenon with motion estimation process while passing technique and floating measurement is configured by discrete cosine transform (DCT) to reduce computational complexity which is implemented in this video codec. While delay of bits in encoded buffer side especially in real-time state is being controlled to produce the video with high quality and maintenance a low buffering delay. Our results show the performance accuracy gain with better achievement in all the above processes in an encouraging mode.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
• /
• pp.358-360
• /
• 2004

The digital images contain a significant amount of redundancy and require a large amount of data for their storage and transmission. Therefore, the image compression is necessary to treat digital images efficiently. The goal of image compression is to reduce the number of bits required for their representation. The image compression can reduce the size of image data using contractive mapping of original image. Among the compression methods, the mapping is affine transformation to find the block(called range block) which is the most similar to the original image. In this paper, we applied the neural network(SOM) in encoding. In order to improve the performance of image compression, we intend to reduce the similarities and unnecesaries comparing with the originals in the codebook. In standard image coding, the affine transform is performed with eight isometries that used to approximate domain blocks to range blocks.

• 전자공학회논문지B
• /
• 제31B권10호
• /
• pp.130-139
• /
• 1994

Video compression algorithms are based on removing spatial and/or temproal redundancy inherent in image sequences by predictive(DPCM) encoding, transform encoding, or a combination of predictive and transform encoding. In this paper, each 8$\times$8 DCT coefficient of DFD(displaced frame difference) is adaptively quantized by one of the four quantizers depending on total distortion level, which is determined by characteristics of HVS(human visual system) and buffer status. Therefore, the number of possible quantizer selection vectors(patterns) is 4$^{64}$. If this vectors are coded, toomany bits are required. Thus, the quantizer selection vectors are limited to 2048 for Y and 512 for each U, V by the proposed method using SWAD(sum of weighted absolute difference) for discriminating vectors. The computer simulation results, using the codebook vectors which are made by the proposed method, show that the subjective and objective image quality (PSNR) are goor with the limited bit allocation. (17Mbps)

• 한국철도학회논문집
• /
• 제8권1호
• /
• pp.1-5
• /
• 2005

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit has been successfully applied to the inductively coupled passive RFTD system working at a frequency of 13.56㎒ in order to process the detection of logical faults more fast and the system has been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates about 15％ In the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• 전기학회논문지
• /
• 제62권1호
• /
• pp.120-126
• /
• 2013

This paper proposes a novel scheme of fault detection and self-recovery for space-borne dual ring counters subject to transient faults. The considered ring counter is equipped with hardware redundancy, but it has a limited output domain where direct access to the current state is unavailable. We employ the theory of corrective control to detect any transient fault occurring to the counter bits and to realize immediate self-recovery of the ring counter back to the normal state. The structure of the fault-tolerant controller is designed to be minimal regardless of the counter size. To validate the applicability, we implement the proposed system on a commercial FGPA board.

• 대한산업공학회지
• /
• 제21권2호
• /
• pp.183-194
• /
• 1995

This research paper describes several possible suggestions which are essential to develop for Built-In-Test(BIT) related systems, such as more precise BIT parameter analysis, sensitivity analysis of the impact of BIT on redundant systems, statistical inference of field data for BIT performance parameters, methods of reducing BIT false alarms, BIT application in industrial automation and remote control, prevent the system from the impact of BIT failure, undetections and false alarms, life cycle cost analysis for BIT. And, it is mainly focused on redundancy technique for solving BIT diagnostic problems. Algorithms for redundant systems : overlapping technique, flexible redundant BITs are presented and case study will be shown based on various experiment.

• 한국콘텐츠학회논문지
• /
• 제12권5호
• /
• pp.1-9
• /
• 2012

디지털 음악과 스마트 폰이 대중화되면서 잡음에 강인한 실시간 음악 핑거프린트 시스템이 다양하게 개발되고 있다. 특히 핑거프린트 알고리즘 중 Multiple Hashing(MLH)은 잡음에 강인하고 정교한 구조로 되어 있다. 본 논문에서는 음악 데이터베이스로부터 질의 및 응답의 정확도를 개선하기 위해 에너지 집중필터를 사용하고 연속성과 중복성을 제거하는 통계적 필터를 제안한다. 에너지 집중 필터는 하위 비트에 에너지가 집중되는 Discrite Cosine Transform(DCT)의 특징을 이용하고, 통계적 필터는 검색된 핑거프린트 정보들 사이의 상관관계 특성을 이용한다. 실험 결과로 잡음 환경에서 에너지와 통계적 필터링으로 구성된 제안 알고리즘은 우수성을 보인다. 이는 제안된 필터 엔진으로 Philips Robust Hash(PRH)보다 잡음에 강인하고 Multiple Hashing(MLH)보다 간결한 핑거프린트 시스템을 구성할 수 있다.

• 한국멀티미디어학회논문지
• /
• 제15권4호
• /
• pp.485-491
• /
• 2012

본 논문은 움직임 벡터와 함께 Coding Unit (CU)의 분할 정보를 표현하기 위해 쿼드트리 기반의 Coding Unit Tree (CUT)를 제안한다. 새로운 동영상 국제 표준안인 High Efficiency Video Coding (HEVC)는 높은 압축 효율을 위해 다양한 새로운 기술들을 채택하였다. 그리고 CU, prediction Unit (PU), 와 Transform Unit (TU)라는 분할 개념을 도입하였다. 그중 기본 부호화 단위인 CU는 H.264/AVC의 매크로 블록보다 다양한 크기를 제공하며 계층적인 구조를 가지고 있으며 쿼드트리 기반의 영상을 분할하고 처리한다. 이러한 구조는 유연성과 최적화를 이룰 수 있는 기반을 제공하고 있으나, 분할 정보에 대한 오버헤더가 발생한다. 복잡한 움직임 정보가 발생하면, 해당하는 정보를 전송하기 위해 다양한 신호가 발생한다. 본 논문에서는 이러한 다양한 신호들을 분석하고, 중복되는 정보를 제거하기 위한 알고리즘을 제안한다. 제안하는 알고리즘 은 기본 블록인 $2{\times}2$ 블록을 기준으로 계층적인 구조를 제안한다. 제안하는 알고리즘은 쿼드트리 기반의 타입 코드로 영상을 구조를 나타내고, 대표 값과 잔여 값으로 각 노드의 값을 표현한다. 결과에서 제안하는 알고리즘이 HM1.0보다 13.6% 압축 향상을 보여준다.

• Journal of information and communication convergence engineering
• /
• 제10권1호
• /
• pp.85-90
• /
• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.