• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.366-370
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• 2007

Nano-scopic holes which are distributed densely and uniformly were fabricated on $SiO_2$ surface. Self-assembling resists were used to produce a layer of uniformly distributed parallel poly methyl methacrylate (PMMA) cylinders in a polystyrene (PS) matrix. The PMMA cylinders were degraded and removed by acetic acid rinsing. Subsequently, PS nanotemplates were fabricated. The patterned holes of PS template were approximately $8{\sim}30\;nm$ wide, 40 nm deep, and 60 nm apart. The porous PS template was used as a dry etching mask to transfer the pattern of PS template into the silicon oxide thin film during reactive ion etching (RIE) process. The sizes of the patterned holes on $SiO_2$ layer were $9{\sim}33\;nm$. After pattern transfer by RIE, uniformly distributed holes of which size were in the range of $6{\sim}22\;nm$ were fabricated on Si substrate. Sizes of the patterned holes were controllable by PMMA molecular weight.

• Applied Chemistry for Engineering
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• v.17 no.3
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• pp.327-330
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• 2006

We investigated the usefulness of $NbO_{x}$ nanopillars as an etching mask of dry etching for the formation of Si nanodot arrays. The $NbO_{x}$ nanopillar arrays were prepared by the anodic aluminum oxidation process of Al and Nb thin films. The etch rate and etch profile of $NbO_{x}$ nanopillar arrays were examined by varying the experimental conditions such as the concentration of etch gas, coil rf power, and dc bias voltage in the reactive ion etch system using the inductively coupled plasma. As the concentration of $Cl_{2}$ gas increased, the etch rate of $NbO_{x}$nanopillars decreased. With increasing coil rf power and dc bias voltage, the etch rates were found to increase. The etch characteristics and etch mechanism of $NbO_{x}$ nanopillars were investigated by varying the etch time under the selected etch conditions.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.8
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• pp.1236-1241
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• 2017

We deposited Al-doped ZnO (ZnO:Al) thin films on glass substrates ($200mm{\times}200mm$) by using in-line magnetron sputtering system. Effects of various deposition parameters such as working pressure, deposition power and substrate temperature on optoelectronic characteristics including surface-texture etching profiles were carefully investigated in this study. We found that relatively low working pressure and high deposition power offered to obtain enhanced conductivity and optical transmittance. Haze properties showed similar trend with the transmittance. Furthermore, surface-texture etching study exhibited good morphologies when the films were deposited at $200-300^{\circ}C$. On the basis of these optimizations, we could find the deposition region that produces highly transparent and conductive properties including efficient light scattering capability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.62-65
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• 2001

$SrBi_2Ta_2O_{9}$ thin films were etched in inductively coupled $Cl_{2}$/$CF_{4}$/Ar plasma. The maximum etch rate was 1060 $\AA\textrm{m}$/min in $Cl_{2}$/$CF_{4}$/Ar (80). The chemical reactions on the etched surface were studied with x-ray photoelectron spectroscopy. The etching of SBT thin films in $Cl_{2}$/$CF_{4}$/Ar were etched by chemically assisted reactive ion etching. The small addition of $Cl_2$ into $CF_4$(20)/Ar(80) plasma will decrease the fluorine radicals and the increase Cl radical.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.77-79
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• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.2
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• pp.25-32
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• 1998

In this paper, we report the result of the three-dimensional topography simultor, 3D-SURFILER(SURface proFILER) for the simulation of topographical evalution of the surface, curing a plasma etching process. We employed cell-removal algorithm to represent the topographical evoluation of the surface. The visibility with shadow effect was developed and applied to the spillover algorithm. To demonstrate the capability of 3D-SURFILER, we compared with simulated profiles with the SEM picture for dry and reactive ion etching(RIE) of the Si$_{3}$N$_{4}$ film and Pt film.

• Proceedings of the Korean Radioactive Waste Society Conference
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• 2005.11b
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• pp.300-315
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• 2005

Recently plasma surface-cleaning or surface-etching techniques have been focused in the respect of decontamination of spent or used nuclear parts and equipment. In this study decontamination rate of metallic cobalt surface was experimentally investigated via its surface etching rate with a $CF_4-O_2$ mixed gas plasma and metallic surface wastes of cobalt oxides were simulated and decontaminated with $NF_3$ - Ar mixed gas plasma. Experimental results revealed that a mixed etchant gas with about $80{\%}\;CF_4-20{\%}\;O_2$ gives the highest reaction rate of cobalt disk and the rate reaches with a negative 300 DC bias voltage up to $0.43\;{\mu}m$/min at $380^{\circ}C$ and $20{\%}\;NF_3-80\%$ Ar mixed gas gives $0.2\;{\mu}m$/min of reaction rate of cobalt oxide film.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2004.03a
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• pp.588-592
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• 2004

This paper presents the preliminary fabrication results of colloid thrusters which can provide thrust of the order of micro to milli-Newtons. MEMS technology has been used for fabrication, and four essential fabrication techniques - deep etching with nested masks, isotropic plasma etching, anisotropic reactive ion etching, and direct fusion wafer bonding - have been newly developed. Among diverse models which have been designed and fabricated, the fabrication results of 4-inch wafer-based colloid thrusters are presented.

• Journal of the Optical Society of Korea
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• v.18 no.3
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• pp.283-287
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• 2014

Square lattice nano-hole arrays with diameters and periodicities of 200 and 500 nm, respectively, are fabricated on InGaN/GaN blue light emitting diodes (LEDs) using electron-beam lithography and inductively coupled plasma reactive ion etching processes. Cathodoluminescence (CL) investigations show that light emission intensity from the LEDs with the nano-hole arrays is enhanced compared to that from the planar sample. The CL intensity enhancement factor decreases when the nano-holes penetrate into the multiple quantum wells (MQWs) due to the plasma-induced damage and the residues. Wet chemical treatment using KOH solution is found to be an effective method for light extraction from the nano-patterned LEDs, especially, when the nano-holes penetrate into the MQWs. About 4-fold CL intensity enhancement factor is achieved by the KOH treatments after the dry etching for the sample with a 250-nm deep nano-hole array.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.79-79
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• 1999

The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.