• 한국재료학회지
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• 제5권1호
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• pp.42-54
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• 1995

$Ta_2O_5$박막은 고유전율의 특성으로 차세대 DRAM캐패시터 물질로 유망받고 있는 물질이다. 본 연구에서는 p-type(100)Si 웨이퍼 위에 열 MOCVD 방법으로 $Ta_2O_5$박막을 성장시켰으며 기판온도, 버블러 온도, 반응압력의 조업조건이 미치는 영향을 고찰하엿다. 증착된 박막은 SEM, XRD, XPS, FT-IR, AES, TEM, AFM을 이용하여 분석하였으며 질소나 산소 분위기의 furnace 열처리 (FA)와 RTA(Rapid Thermal Annealing)를 통하여 열처리 효과를 살펴보았다. 반응온도에 따른 증착속도는 300 ~ $400 ^{\circ}C$ 범위에서 18.46kcal/mol의 활성화 에너지를 가지는 표면반응 율속단계와 400 ~ $450^{\circ}C$ 범위에서 1.9kcal/mol의 활성화 에너지를 가지는 물질전단 율속단계로 구분되었다. 버블러 온도는 $140^{\circ}C$일때 최대의 증착속도를 보였다. 반응압력에 따른 증착속도는 3torr에서 최대의 증착속도를 보였으나 굴절율은 0.1-1torr사이에 $Ta_2O_5$의 bulk값과 비슷한 2.1정도의 양호한 값이 얻어졌다. $400^{\circ}C$에서 층덮힘은 85.71%로 매우 양호하게 나타났으며 몬테카를로법에 의한 전산모사 결과와의 비교에 의해서 부착계수는 0.06으로 나타났다. FT-IR, AES, TEM 분석결과에 의하여 Si와 $Ta_2O_5$ 박막 계면의 산화막 두께는 FA-$O_{2}$ > RTA-$O_{2}$ ~ FA-$N_{2}$ > RTA-$N_{2}$ 순으로 성장하였다. 하지만 질소분위기에서 열처리한 박막은 산소분위기의 열처리경우에 비해 박막내의 산소성분의 부족으로 인한 그레인 사이의 결함이 많이 관찰되었다.

• 한국재료학회지
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• 제3권1호
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• pp.12-18
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• 1993

단결정 실리콘위에 스퍼터법으로 증착된 티타니움막을 급속가열로에서 고상반응에 의해 형성시킨 면저항 1.2 ohm/sq. 내외의 TiS$i_2$ 박막에 있어서 열안정성을 상부절연막의 유무 및 종류에 따라 조사하였다. 상부절연막은 상압 CVD로 증착한 USG(Undoped Silicate Glass, Si$i_2$) 막과 플라즈마 CVD법으로 증착한 PE-SiN(S$i_3$$N_4$)막을 사용했다. 열안정성 평가는 90$0^{\circ}C$에서 시간을 달리하여 TiS$i_2$막, PE-SiN막, USG막의 스트레스는 각각 1.3${\times}{10^{9}}$, 1.25 ${\times}{10^{10}}$, 2.26 ${\times}{10^{10}}$ dyne/c$m^2$의 인장응력을 나타내었다. 응집현상은 TiS$i_2$의 응집현상은 Nabarro-Herring 마이크로 크리프에 의한 원자의 확산관점에서 검토되었다.

• The Korean Journal of Ceramics
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• 제6권2호
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• pp.138-142
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• 2000

Thin film $LiNbO_3$MFS (metal-ferroelectric-semiconductor) capacitor showed improved characteristics such as low interface trap density, low interaction with Si substrate, and large remanent polarization. This paper reports ferroelectric $LiNbO_3$thin films grown directly on p-type Si (100) substrates by 13.56 MHz RF magnetron sputtering system for FRAM (ferroelectric random access memory) applications. RTA (rapid thermal anneal) treatment was performed for as-deposited films in an oxygen atmosphere at $600^{\circ}C$ for 60sec. We learned from X-ray diffraction that the RTA treated films were changed from amorphous to poly-crystalline $LiNbO_3$which exhibited (012), (015), (022), and (023) plane. Low temperature film growth and post RTA treatments improved the leakage current of $LiNbO_3$films while keeping other properties almost as same as high substrate temperature grown samples. The leakage current density of $LiNbO_3$films decreased from $10^{-5}$ to $10^{-7}$A/$\textrm{cm}^2$ after RTA treatment. Breakdown electric field of the films exhibited higher than 500 kV/cm. C-V curves showed the clockwise hysteresis which represents ferroelectric switching characteristics. Calculated dielectric constant of thin film $LiNbO_3$illustrated as high as 27.9. From ferroelectric measurement, the remanent polarization and coercive field were achieved as 1.37 $\muC/\textrm{cm}^2$ and 170 kV/cm, respectively.

• 한국전기전자재료학회논문지
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• 제19권7호
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• pp.605-610
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• 2006

We have investigated $Al_{0.25}Ga_{0.75}As/In_{0.2}Ga_{0.8}As$ structures for pseudomorphic high electron mobility transistor(pHEMT), which were grown by molecular beam epitaxy(MBE) and consequently annealed by rapid thermal anneal(RTA), using Hall measurement, photoluminescence, and transmission electron microscopy (TEM). According to intensity and full-width at half maximum maintained stable at the same energy level, the quantized energy level in $Al_{0.25}Ga_{0.75}As/In_{0.2}Ga_{0.8}As$ quantum wells was independent of the RTA conditions. However, the Hall mobility was decreased from $6,326cm^2/V.s\;to\;2,790cm^2/V.s\;and\;2,078cm^2/V.s$ after heat treatment respectively at $500^{\circ}C\;and\;600^{\circ}C$. The heat treatment which is indispensable during the fabrication procedure would cause catastrophic degradation in electrical transport properties. TEM observation revealed atomically non-uniform interfaces, but no dislocations were generated or propagated. From theoretical consideration about the mobility changes owing to inter-diffusion, the degraded mobility could be directly correlated to the interface scattering as long as samples were annealed below $600^{\circ}C$ lot 1 min.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 춘계학술대회
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• pp.250-253
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• 2007

An evaporated Ti/Pd/Ag contact system is most widely used to make high-efficiency silicon solar cells, however, the system is not cost effective due to expensive materials and vacuum techniques. Commercial solar cells with screen-printed contacts formed by using Ag paste suffer from a low fill factor and a high shading loss because of high contact resistance and low aspect ratio. Low-cost Ni and Cu metal contacts have been formed by using electroless plating and electroplating techniques to replace the Ti/Pd/Ag and screen-printed Ag contacts. Ni/Cu alloy is plated on a silicon substrate by electro-deposition of the alloy from an acetate electrolyte solution, and nickel-silicide formation at the interface between the silicon and the nickel enhances stability and reduces the contact resistance. It was, therefore, found that nickel-silicide was suitable for high-efficiency solar cell applications. The Ni contact was formed on the front grid pattern by electroless plating followed by anneal ing at $380{\sim}400^{\circ}C$ for $15{\sim}30$ min at $N_{2}$ gas to allow formation of a nickel-silicide in a tube furnace or a rapid thermal processing(RTP) chamber because nickel is transformed to NiSi at $380{\sim}400^{\circ}C$. The Ni plating solution is composed of a mixture of $NiCl_{2}$ as a main nickel source. Cu was electroplated on the Ni layer by using a light induced plating method. The Cu electroplating solution was made up of a commercially available acid sulfate bath and additives to reduce the stress of the copper layer. The Ni/Cu contact was found to be well suited for high-efficiency solar cells and was successfully formed by using electroless plating and electroplating, which are more cost effective than vacuum evaporation. In this paper, we investigated low-cost Ni/Cu contact formation by electroless and electroplating for crystalline silicon solar cells.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.438-439
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• 2013

Microelectronic devices의 접촉저항의 향상을 위해 Metal silicides의 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 지난 수십년에 걸쳐, Ti silicide, Co silicide, Ni silicide 등에 대한 개발이 이루어져 왔으나, 계속적인 저저항 접촉 소재에 대한 요구에 의해 최근에는 Rare earth silicide에 관한 연구가 시작되고 있다. Rare-earth silicide는 저온에서 silicides를 형성하고, n-type Si과 낮은 schottky barrier contact (~0.3 eV)를 이룬다. 또한, 비교적 낮은 resistivity와 hexagonal AlB2 crystal structure에 의해 Si과 좋은 lattice match를 가져 Si wafer에서 high quality silicide thin film을 성장시킬 수 있다. Rare earth silicides 중에서 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 낮은 schottky barrier 응용에서 쓰이고 있다. 이로 인해, n-channel schottky barrier MOSFETs의 source/drain으로써 주목받고 있다. 특히 ytterbium과 molybdenum co-deposition을 하여 증착할 경우 thin film 형성에 있어 안정적인 morphology를 나타낸다. 또한, ytterbium silicide와 마찬가지로 낮은 면저항과 electric work function을 갖는다. 그러나 ytterbium silicide에 molybdenum을 화합물로써 높은 농도로 포함할 경우 높은 schottky barrier를 형성하고 epitaxial growth를 방해하여 silicide film의 quality 저하를 야기할 수 있다. 본 연구에서는 ytterbium과 molybdenum의 co-deposition에 따른 silicide 형성과 전기적 특성 변화에 대한 자세한 분석을 TEM, 4-probe point 등의 다양한 분석 도구를 이용하여 진행하였다. Ytterbium과 molybdenum을 co-deposition하기 위하여 기판으로 $1{\sim}0{\Omega}{\cdot}cm$의 비저항을 갖는 low doped n-type Si (100) bulk wafer를 사용하였다. Native oxide layer를 제거하기 위해 1%의 hydrofluoric (HF) acid solution에 wafer를 세정하였다. 그리고 고진공에서 RF sputtering 법을 이용하여 Ytterbium과 molybdenum을 동시에 증착하였다. RE metal의 경우 oxygen과 높은 반응성을 가지므로 oxidation을 막기 위해 그 위에 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, 진공 분위기에서 rapid thermal anneal(RTA)을 이용하여 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium silicides를 형성하였다. 전기적 특성 평가를 위한 sheet resistance 측정은 4-point probe를 사용하였고, Mo doped ytterbium silicide와 Si interface의 atomic scale의 미세 구조를 통한 Mo doped ytterbium silicide의 형성 mechanism 분석을 위하여 trasmission electron microscopy (JEM-2100F)를 이용하였다.

• Transactions on Electrical and Electronic Materials
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• 제9권1호
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• pp.6-11
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• 2008

In this study, we investigated effects of hydrogen annealing (HA) and plasma nitridation (PN) applied in order to improve $Si/SiO_2$ interface characteristics of TiN metal gate. In result, HA and PN showed a positive effect decreasing number of interface state $(N_{it})$ respectively. After FN stress for verifying reliability, however, we identified rapid increase of $N_{it}$ for TiN gate with HA, which is attributed to hydrogen related to a change of $Si/SiO_2$ interface characteristic. In contrast to HA, PN showed an improved Nit and gate oxide leakage characteristic due to several possible effects, such as blocking of Chlorine (Cl) diffusion and prevention of thermal reaction between TiN and $SiO_2$.

• 한국산학기술학회논문지
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• 제6권3호
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• pp.273-277
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• 2005

새로이 제안된 15nm-Ni/15nm-Co의 적층구조로부터 제조된 NiCo 복합실리사이드를 실제 디바이스에 채용하기 위해, $SiO_2$ 스페이서를 가진 폴리실리콘 게이트 선폭이 $0.25\~l.5um$까지 변화하는 테스트그룹을 이용하여 30초-RTA를 이용한 실리사이드화 온도를 $700^{\circ}C\~1100^{\circ}C$까지 변화시키면서 이때 cleaning전후의 잔류금속의 생성모습을 확인하였다. RTA온도가 올라갈수록 $SiO_2$로 구성된 필드와 스페이서 상부와, 실리사이드가 형성된 게이트 상부에 $0.25{\mu}m$정도의 단축직경을 가진 타원형 잔류금속이 미로형 또는 게이트 방향으로 생성되는 특징이 있었고 동시에 응집이 많아지는 현상이 있었다. 응집이 많을수록 하부 절연층과의 반응도가 증가하여 절연특성이 저하될 수 있었고 과도한 습식제거 공정을 오래하여야 하므로 실험범위 내에서 가급적 저온 실리사이드화 열처리가 바람직하였다.

• 한국전기전자재료학회논문지
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• 제22권9호
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• pp.717-723
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• 2009

Ni/Al ('/' denotes deposition sequence) contacts were deposited on Al-implanted 4H-SiC for ohmic contact formation, and the conduction properties were characterized and compared with those of Ni-only contacts. The thicknesses of the Ni and Al thin film were 30 nm and 300 nm, respectively, and the films were sequentially deposited bye-beam evaporation without vacuum breaking. Rapid thermal anneal (RTA) temperature was varied as follows : $840^{\circ}C$, $890^{\circ}C$, and $940^{\circ}C$. The specific contact resistivity of the Ni contact was about $^{\sim}2\;{\pm}\;10^{-2}\;{\Omega}{\cdot}cm^2$, However, with the addition of Al overlayer, the specific contact resistivity decreased to about $^{\sim}2\;{\pm}\;10^{-4}\;{\Omega}{\cdot}cm^2$, almost irrespective of RTA temperature. X-ray diffraction (XRD) analysis of the Ni contact confirmed the existence of various Ni silicide phases, while the results of Ni/Al contact samples revealed that Al-contaning phases such as $Al_3Ni$, $Al_3Ni_2$, $Al_4Ni_3$, and $Ab_{3.21}Si_{0.47}$ were additionally formed as well as the Ni silicide phases. Energy dispersive spectroscopy (EDS) spectrum showed interfacial reaction zone mainly consisting of Al and Si at the contact interface, and it was also shown that considerable amounts of Si and C have diffused toward the surface. This indicates that contact resistance lowering of the Ni/Al contacts is related with the formation of the formation of interfacial reaction zone containing Al and Si. From these results, possible mechanisms of contact resistance lowering by the addition of Al were discussed.

• ETRI Journal
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• 제16권1호
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• pp.45-57
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• 1994

The effects of reactive ion etching (RIE) of $SiO_2$ layer in $CHF_3/C_2F_6$ on the underlying Si surface have been studied by X-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometer, Rutherford backscattering spectroscopy, and high resolution transmission electron microscopy. We found that two distinguishable modified layers are formed by RIE : (i) a uniform residue surface layer of 4 nm thickness composed entirely of carbon, fluorine, oxygen, and hydrogen with 9 different kinds of chemical bonds and (ii) a contaminated silicon layer of about 50 nm thickness with carbon and fluorine atoms without any observable crystalline defects. To search the removal condition of the silicon surface residue, we monitored the changes of surface compositions for the etched silicon after various post treatments as rapid thermal anneal, $O_2$, $NF_3$, $SF_6$, and $Cl_2$ plasma treatments. XPS analysis revealed that $NF_3$ treatment is most effective. With 10 seconds exposure to $NF_3$ plasma, the fluorocarbon residue film decomposes. The remained fluorine completely disappears after the following wet cleaning.