• Journal of Power Electronics
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• 제19권1호
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• pp.99-107
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• 2019

This study proposes a new modulation strategy to deal with unbalanced output voltage that is based on three-level neutral-point-clamped cascaded rectifiers. The fundament idea is to reallocate the value of the voltage levels generated by each of the modules on the basis of space vector pulse width modulation. This proposed modulation strategy can reduce the switching frequency while maintaining the mutual-module voltage balance. First, an analysis of unbalanced output voltage is reflected. Then a new modulation strategy is introduced in detail. Internal module capacitor voltages are balanced by the selection of redundant vectors. Moreover, the voltage balance ability is calculated. Finally, the feasibility of this modulation strategy is verified through experimental results.

• The Transactions of the Korean Institute of Electrical Engineers D
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• 제55권10호
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• pp.458-463
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• 2006

The purpose of this work is to investigate the fundamental properties of the gradual muscle force potentiation. We investigated the dependence of force potentiation on both the pulse-amplitude and the pulse-duration with different ramp-up time. The experimental results showed that the force increment ratio (FIR) during constant electrical stimulation decreased with pulse-amplitude and also with pulse-duration. The FIR was greater with short ramp-up time in both the pulse-amplitude and pulse-width modulation. The feasible mechanism might be that the myosin light chain phosphorylation induces the force potentiation and it occurs only in the fast type muscle fibers which are recruited first. These observations indicate that muscle potentiation must be understood well for the accurate control of muscle force.

• Journal of Power Electronics
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• 제14권1호
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• Journal of Power Electronics
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• 제14권6호
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• pp.1197-1207
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• 2014

Common-mode voltage (CMV) causes overvoltage stress to winding insulation and damages AC motors. CMV with high dv/dt causes leakage currents, which create noise problems for equipment installed near the converter. This study proposes a new pulse-width modulation (PWM) strategy for three-level T-type NPC inverters. This strategy substantially eliminates CMV. The principle for selecting suitable triangle carrier signals for the three-level T-type NPC is described. The proposed method can mitigate the peak value of CMV by 50% compared with the phase disposition pulse-width modulation method. Furthermore, the proposed method exhibits better harmonic spectrum and lower root mean square value for the CMV than those of the reduced-CMV method on the basis of the phase opposition disposition PWM scheme with modulation index higher than 0.5. The proposed modulation can easily be implemented using software without any additional hardware modifications. Both simulation and experimental results demonstrate that the proposed carrier phase-shift PWM method has good output waveform performance and reduces CMV.

• The Transactions of the Korean Institute of Electrical Engineers B
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• 제49권12호
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• pp.813-820
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• 2000

A technique to suppress the low frequency ripple voltage of the DC output in three phase buck diode converter is presented in this paper. The proposed pulse frequency modulation methods and duty ratio modulation methods are employed to regulate the output voltage of the buck diode converter and guarantee zero-current-switching(ZCS) of the switch over the wide load range. The proposed control methods used in this paper provide generally good performance such as low THD of the input line current and unity power factor. In addition, control methods can be effectively used to suppress the low frequency ripple voltage appeared in the dc output voltage. The harmonic injection technique illustrates its validity and effectiveness through the simulations and experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제32권12A호
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• pp.1244-1250
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• 2007

User cooperation provides high reliability in wireless communication systems by employing relay nodes to transmit the same information. In this paper, a bit error rate (BER) study is presented for decode-and-forward (DF) relaying for user cooperation in independent and identically distributed Rayleigh fading channels. For an arbitrary number of relays, exact and closed-form expressions of the BER are proposed for M-ary PAM (Pulse Amplitude Modulation), QAM (Quadrature Amplitude Modulation) and PSK (Phase Shift Keying), respectively. It is also shown that the analytic results are perfectly matched with the simulated ones.

• Journal of Electrical Engineering and Technology
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• 제5권2호
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• pp.299-306
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• 2010

This paper proposes a new doubly-fed induction generator (DFIG) system using a matrix converter controlled by direct duty ratio pulse-width modulation (DDPWM) scheme. DDPWM is a recently proposed carrier based modulation strategy for matrix converters which employs a triangular carrier and voltage references in a voltage source inverter. By using DDPWM, the matrix converter can directly and effectively generate rotor voltages following the voltage references within the closed control loop. The operation of the proposed DFIG system was verified through computer simulation and experimental works with a hardware simulator of a wind power turbine, which was built using a motor-generator set with vector drive. The simulation and experimental results confirm that a matrix converter with a DDPWM modulation scheme can be effectively applied for a DFIG wind power system.

• ETRI Journal
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• 제30권1호
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• pp.161-163
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• 2008

An M-ary bi-orthogonal modulation scheme for ultra-wideband (UWB) systems capable of narrowband interference (NBI) suppression is proposed in this letter. We utilize a set of bi-orthogonal pulse series to achieve NBI suppression. Through analysis and simulation, we verify that the proposed scheme can suppress NBIs effectively.

• Proceedings of the KIPE Conference
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• 전력전자학회 2020년도 전력전자학술대회
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• pp.106-108
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• 2020

This paper introduces a new pulse-width modulation (PWM) method to reduce common-mode voltages (CMVs) and compare its performance with other reduced CMV-PWM (RCMV-PWM) methods. To avoid the use of zero-vectors which cause high CMV peaks, the introduced method splits every reference vector into two vectors such that the peak-to-peak magnitude of CMV is reduced by one-third of conventional space-vector PWM (SVPWM). The performance of RCMV-PWMs altered by the modulation index are analyzed with simulation results.

• The Journal of the Korea Contents Association
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• 제10권2호
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.