• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.9
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• pp.3266-3285
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• 2014

With limited computing and storage resources, many network applications of encryption algorithms require low power devices and fast computing components. CHESS-64 is designed by employing simple key scheduling and Data-Dependent operations (DDO) as main cryptographic components. Hardware performance for Field Programmable Gate Arrays (FPGA) and for Application Specific Integrated Circuits (ASIC) proves that CHESS-64 is a very flexible and powerful new cipher. In this paper, the security of CHESS-64 block cipher under related-key differential cryptanalysis is studied. Based on the differential properties of DDOs, we construct two types of related-key differential characteristics with one-bit difference in the master key. To recover 74 bits key, two key recovery algorithms are proposed based on the two types of related-key differential characteristics, and the corresponding data complexity is about $2^{42.9}$ chosen-plaintexts, computing complexity is about $2^{42.9}$ CHESS-64 encryptions, storage complexity is about $2^{26.6}$ bits of storage resources. To break the cipher, an exhaustive attack is implemented to recover the rest 54 bits key. These works demonstrate an effective and general way to attack DDO-based ciphers.

• Journal of information and communication convergence engineering
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• v.20 no.3
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• pp.166-173
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• 2022

Recently, studies have been conducted on intelligent transportation systems (ITS) that provide safety and convenience to humans. Systems that compose the ITS adopt architectures that applied the cloud computing which consists of a high-performance general-purpose processor or graphics processing unit. However, an architecture that only used the cloud computing requires a high network bandwidth and consumes much power. Therefore, applying edge computing to ITS is essential for solving these problems. In this paper, we propose an edge artificial intelligence (AI) device based ITS. Edge AI which is applicable to various systems in ITS has been applied to license plate recognition. We implemented edge AI on a field-programmable gate array (FPGA). The accuracy of the edge AI for license plate recognition was 0.94. Finally, we synthesized the edge AI logic with Magnachip/Hynix 180nm CMOS technology and the power consumption measured using the Synopsys's design compiler tool was 482.583mW.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.2
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• pp.97-104
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• 2011

This paper deals with the quick and precise disaster prevention automation system (DPAS) based on information communication technology (IT) that detects fire and disasters in the building automatically and quickly and then activates the facilities to extinguish fire and disasters, monitoring such situation in a real time through wire-wireless communication network. The proposed DPAS is applied a programmable logic controller (PLC) of one-chip type which is smallsize and lightweight and also has highly sensitive-precise reliabilities. The one-chip type PLC analyzes detected signals from sensors in a case of fire and disasters, then activates fire extinguishing facilities for rapid suppression. The detected data is also transferred to a remote situation room through wire-wireless network of RS232c and bluetooth communication. The transferred data sounds an emergency alarm signal, and operates a monitoring program. The proposed DPAS based on IT will minimize the life and wealth loss from rapid measures while prevents fire and disasters.

• The KIPS Transactions:PartC
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• v.11C no.7 s.96
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• pp.951-958
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• 2004

Nowadays NGN is developed for supporting the e-Commerce, Internet trading, e-Government, e-mail, virtual-life and multimedia. Internet gives us the benefit of remote access to the information but causes the attacks that can break server and modify information. Since 2000 Nimda, Code Red Virus and DSoS attacks are spreaded in Internet. This attack programs make tremendous traffic packets on the Internet. In this paper, we designed and developed the Bandwidth Controller in the gateway systems against the bandwidth saturation attacks. This Bandwidth con-troller is implemented in hardware chipset(FPGA) Virtex II Pro which is produced by Xilinx and acts as a policing function. We reference the TBF(Token Bucket Filter) in Linux Kernel 2.4 and implemented this function in HDL(Hardware Description Language) Verilog. This HDL code is synthesized in hardware chipset and performs the gigabit traffic in real time. This policing function can throttle the traffic at the rate of band width controlling policy in bps speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.6
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• pp.387-396
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• 2014

Recently, there have been continuous efforts and progresses regarding the research on diverse network control and management platforms for SDN (Software Defined Networking). SDN is defined as a new technology to enable service providers/network operators easily to control and manage their networks by writing a simple application program. In SDN, incomplete or malicious programmable entities could cause break-down of underlying networks shared by heterogeneous devices and stake-holders. In this sense, any misunderstanding or diverse interpretations should be completely avoided. This paper proposes a new framework for SDN application verification and a prototype based on the formal method, especially with process algebra called pACSR which is an extended version of Algebra of Communicating Shared Resources (ACSR).

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.10
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• pp.4865-4885
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• 2019

We propose a FPGA based design that performs real-time power-efficient analysis of heterogeneous sensor data using adaptive ANN on edge gateway of smart military wearables. In this work, four independent ANN classifiers are developed with optimum topologies. Out of which human activity, BP and toxic gas classifier are multiclass and ECG classifier is binary. These classifiers are later integrated into a single adaptive ANN hardware with a select line(s) that switches the hardware architecture as per the sensor type. Five versions of adaptive ANN with different precisions have been synthesized into IP cores. These IP cores are implemented and tested on Xilinx Artix-7 FPGA using Microblaze test system and LabVIEW based sensor simulators. The hardware analysis shows that the adaptive ANN even with 8-bit precision is the most efficient IP core in terms of hardware resource utilization and power consumption without compromising much on classification accuracy. This IP core requires only 31 microseconds for classification by consuming only 12 milliwatts of power. The proposed adaptive ANN design saves 61% to 97% of different FPGA resources and 44% of power as compared with the independent implementations. In addition, 96.87% to 98.75% of data throughput reduction is achieved by this edge gateway.

• Journal of Internet Computing and Services
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• v.22 no.2
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• pp.11-17
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• 2021

Software-defined networking provides a programmable and flexible way to manage the network by separating the control plane from data plane. However, the limited switch memory restricts the number of flow entries in the flow table used to forward packets. This leads to flow table overflow and flow entry reinstallation, which severely degrade the network performance. Therefore, this paper proposes a comprehensive policy for timely eviction of inactive flow entries to optimally maintain flow tables usage. In particular, statistics of user datagram protocol flow entries are periodically sampled to enable the inactive entries to be evicted early. Through traffic-based experiments, we found that the proposed system reduces the number of overflow occurrences and flow entries reinstallation compared to the random and FIFO policies.

• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

• Journal of Advanced Navigation Technology
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• v.19 no.5
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• pp.423-432
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• 2015

This paper shows that design, manufacture and the performance of FC-NIC (fibre channel network interface card) for network unit configuration which is based on one of the 5 main configuration items of the common functional module for IMA (integrated modular Avionics) architecture. Especially, FC-NIC uses zynq SoC (system on chip) for host load reductions. The host merely transmit FC destination address, source memory location and size information to the FC-NIC. After then the FC-NIC read the host memory via DMA (direct memory access). FC upper layer protocol and sequence process at local processor and programmable logic of FC-NIC zynq SoC. It enables to free from host load for external communication. The performance of FC-NIC shows average 5.47 us low end-to-end latency at 2.125 Gbps line speed. It represent that FC-NIC is one of good candidate network for IMA.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.9
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• pp.35-46
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• 2011

Future Internet should support more efficient mobility management, flexible traffic engineering and various emerging new services. So, lots of traffic engineering techniques have been suggested and developed, but it's impossible to apply them on the current running commercial Internet. To overcome this problem, OpenFlow protocol was proposed as a technique to control network equipments using network controller with various networking applications. It is a software defined network, so researchers can verify their own traffic engineering techniques by applying them on the controller. In addition, for high-speed packet processing in the OpenFlow network, programmable NetFPGA card with four 1G-interfaces and commercial Procurve OpenFlow switches can be used. In this paper, we implement an OpenFlow test-bed using hardware-accelerated NetFPGA cards and Procurve switches on the KREONET, and implement CSPF (Constraint-based Shortest Path First) algorithm, which is one of popular QoS routing algorithms, and apply it on the large-scale testbed to verify performance and efficiency of multimedia traffic engineering scheme in Future Internet.