• Journal of Convergence for Information Technology
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• v.9 no.2
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• pp.85-93
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• 2019

There is currently no recognized standard for the size of lifts. Each elevator manufacturer sets the maximum allowable floor area that meets the capacity calculation standard of the elevator using the maximum used car floor area, which is defined by EN-CODE and the domestic inspection standard, and determines the elevator size based on their own standards. In this paper, we propose a method to more easily determine the elevator size. To do this, we implemented a program that calculates the size of the elevator by inputting the dimensions of the hoistway. This program will be useful method for quick decision making and elevator installation considering the elevator factors according to the already determined hoistway size of the building and calculating the EN-CODE currently used and the size of the elevator according to domestic inspection standards.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.83-90
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• 2004

In this paper, we proposed a new instruction set(X32Y ISA) with 3 different types of instruction mode. The proposed instruction set organizes 32-bit, 24-bit, 16-bit instruction in order to solves a problem of memory size limitation in an embedded microprocessor. We designed a 32-bit 5 stage pipeline RISC microprocessor based on the X32V ISA. To verify the proposed the X32V ISA and a microprocessor, we estimated a program code size of multimedia application programs using a X32V simulator. In result, we verified that the Light mode and the Ultra Light mode obtains 8%, 27% reduction of a program code size through comparison with the Default mode. The proposed microprocessor was verified all X32V instructions execution at Xilinx FPGA with 33MHz operating frequency,

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1575-1579
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• 1999

Embedded processors often accommodate two instruction sets, a standard instruction set and a compressed instruction set. With the compressed instruction set, code size can be reduced while instruction count (and consequently execution time) can be increased. To achieve code size reduction without significant increase of execution time, this paper proposes a new compressed instruction set architecture, called TOE (Two Operations Execution). The proposed instruction set format includes the parallel bit that indicates an instruction can be executed simultaneously with the next instruction. To add the parallel bit, TOE instruction format reduces the destination register field. The reduction of the register field limits the number of registers that are accessible by an instruction. To overcome the limited accessibility of registers, TOE adapts non-homogeneous register partition in which registers are divided into multiple subsets, each of which are accessed by different groups of instructions. With non-homogeneous registers, each instruction can access only a limited number of registers, but an entire program can access all available registers. With efficient non-homogeneous register allocator, all registers can be used in a balanced manner. As a result, the increase of code size due to register spills is negligible. Experimental results show that more than 30% of TOE instructions can be executed in parallel without significant increase of code size when compared to existing Thumb instruction set.

• Journal of KIISE:Software and Applications
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• v.32 no.3
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• pp.227-235
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• 2005

In the embedded system domain, both memory requirement and energy consumption are great concerns. To save memory and energy, the 32 bit ARM processor supports the 16 bit Thumb instruction set. For a given program, the Thumb code is typically smaller than the ARM code. However, the limitations of the Thumb instruction set can often lead to generation of poorer quality code. To generate codes with smaller size but a little slower execution speed, Krishnaswarmy suggests a profiling guided selection algorithm at module level for generating mixed ARM and Thumb codes for application programs. The resulting codes of the algorithm give significant code size reductions with a little loss in performance. When the instruction set is selected at module level, some functions, which should be compiled in Thumb mode to reduce code size, are compiled to ARM code. It means we have additional code size reduction chance. In this paper, we propose a profile guided selection algorithm at function level for generating mixed ARM and Thumb codes for application programs so that the resulting codes give additional code size reductions without loss in performance compared to the module level algorithm. We can reduce 2.7％ code size additionally with no performance penalty

• KIPS Transactions on Software and Data Engineering
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• v.4 no.1
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• pp.1-8
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• 2015

Safety critical systems require exhaustive verification of safety properties, because even a single corner-case fault can cause a critical safety failure. However, existing verification approaches are too costly in terms of time and computational resource required, making it hard to be applied in practice. In this paper, we implemented a tool for minimizing the size of the verification target w.r.t. verification properties to check, based on program slicing technique[1]. The efficacy of program slicing using our tool is demonstrated in a case study with a verification target Trampoline[3], which is an open source automotive operating system compliant with OSEK/VDX[2]. Experiments have shown enhanced performance in verification, with a 71% reduction in the size of the code.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.548-551
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• 2003

JSize is a Java equivalent of the Unix size program. The Unix size program analyses an executable file and estimates the size of code and data segment when the file is loaded on memory. Likewise, JSize analyze a Java class file and estimates the size of class area when the file is loaded on memory. This paper presents the principles necessary to estimate the class area size with the information obtained from a class file. An experimental result is included to show the accuracy of estimation the JSize provides.

• Computers and Concrete
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• v.2 no.5
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• pp.345-366
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• 2005

This work presents an assessment of the computational performance of a vector-parallel implementation of probabilistic model for concrete cracking in 3D. This paper shows the continuing efforts towards code optimization as reported in earlier works Paz, et al. (2002a,b and 2003). The probabilistic crack approach is based on the direct Monte Carlo method. Cracking is accounted by means of 3D interface elements. This approach considers that all nonlinearities are restricted to interface elements modeling cracks. The heterogeneity governs the overall cracking behavior and related size effects on concrete fracture. Computational kernels in the implementation are the inexact Newton iterative driver to solve the non-linear problem and a preconditioned conjugate gradient (PCG) driver to solve linearized equations, using an element by element (EBE) strategy to compute matrix-vector products. In particular the paper analyzes code behavior using OpenMP directives in parallel vector processors (PVP), such as the CRAY SV1 and CRAY T94. The impact of the memory architecture on code performance, and also some strategies devised to circumvent this issue are addressed by numerical experiment.

• Journal of Korea Multimedia Society
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• v.5 no.3
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• pp.342-350
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• 2002

The execution speed is not an important factor for Java programming language when implementing small size application program which is executed on the web browser, but it becomes a serious limitation when the huge-size programs are implemented. To overcome this problem, the various research is conducted for translating the Bytecode into the target code which can be implemented in the specific processor by using classical compiling methods. In this research, we have designed and realized an intermediate code translator for the native code generation system with which we can directly generate i386 code from Bytecode to improve the execution speed of Java application programs. The intermediate code translator generates the register-based intermediate code from *.class files which are the intermediate code of Java.

• Journal of the Korea Society of Computer and Information
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• v.18 no.10
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• pp.129-139
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• 2013

Java bytecodes are executed not on target machine but on the Java virtual machines. Since this bytecodes use a higher level representation than binary code, it is possible to decompile most bytecodes back to Java source. Obfuscation is the technique of obscuring code and it makes program difficult to understand. However, most of the obfuscation techniques make the code size and the performance of obfuscated program bigger and slower than original program. In this paper, we proposed an effective Java obfuscation techniques using assignment statements merging that make the source program difficult to understand. The basic approach is to merge assignments statements to append side effects of statement. An additional benefit is that the size of the bytecode is reduced.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.7
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• pp.746-758
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• 1988

This paper proposes a code scheduling algorithm which gives a software solution to the pipeline interlock. This algorithm provides a heuristic solution by recordering the instructions, instead of using hardware interlock mechanism when pipeline interlock prevents the execution of a machine instruction in a pipelined architecture. Program code size and overall execution time can be reduced due to the increased flexibility in the selection of instructions, which is possible from the alleviated ordering restriction on the use of conflict resources.