• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.145-148
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• 2001

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.359-363
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• 2011

To integrate the sensor driver and logic circuits, fabricating down scaled transistors has been main issue. At this research, short channel effects were analyzed after n channel polycrystalline silicon thin film transistor was fabricated at high temperature. As a result, on current, on/off current ratio and transconductance were increased but threshold voltage, electron mobility and s-slope were reduced with a decrease of channel length. When carriers that develop at grain boundary in activated polycrystalline silicon have no gate biased, on current was increased with punch through by drain current. Also, due to BJT effect (parallel bipolar effect) that developed under region of channel by increase of gate voltage on current was rapidly increased.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.364-369
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• 2011

Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by $7.1{\times}10^1$. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.

• Journal of the Korean Physical Society
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• 제73권9호
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• pp.1329-1333
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• 2018

We investigated the mechanism of mobility enhancement after the dehydrogenation process in polycrystalline silicon (poly-Si) thin films. The dehydrogenation process was performed by using an in-situ CVD chamber in a $N_2$ ambient or an ex-situ furnace in air ambient. We observed that the dehydrogenated poly-Si in a $N_2$ ambient had a lower oxygen concentration than the dehydrogenated poly-Si annealed in an air ambient. The in-situ dehydrogenation increased the (111) preferred orientation of poly-Si and reduced the oxygen concentration in poly-Si thin films, leading to a reduction of the trap density near the valence band. This phenomenon gave rise to an increase of the field-effect mobility of the poly-Si thin film transistor.

• 한국재료학회지
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• 제18권9호
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• pp.507-510
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• 2008

Electrical properties of multi-channel metal-induced unilaterally precrystallized polycrystalline silicon thin-film transistor (MIUP poly-Si TFT) devices and circuits were investigated. Although their structure was integrated into small area, reducing annealing process time for fuller crystallization than that of conventional crystal filtered MIUP poly-Si TFTs, the multi-channel MIUP poly-Si TFTs showed the effect of crystal filtering. The multi-channel MIUP poly-Si TFTs showed a higher carrier mobility of more than 1.5 times that of the conventional MIUP poly-Si TFTs. Moreover, PMOS inverters consisting of the multi-channel MIUP poly-Si TFTs showed high dynamic performance compared with inverters consisting of the conventional MIUP poly-Si TFTs.

• ETRI Journal
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• 제30권2호
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• pp.308-314
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• 2008

In this paper, we describe the fabrication of 3.5-inch QCIF active matrix organic light emitting display (AMOLED) panels driven by thin film transistors, which are produced by an ultra-low-temperature polycrystalline silicon process on plastic substrates. The over all processing scheme and technical details are discussed from the viewpoint of mechanical stability and display performance. New ideas, such as a new triple-layered metal gate structure to lower leakage current and organic layers for electrical passivation and stress reduction are highlighted. The operation of a 3.5-inch QCIF AMOLED is also demonstrated.

• 한국진공학회지
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• 제17권5호
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• pp.461-465
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• 2008

적층 박막 내에서의 상변화는 주변 층에 영향을 준다. 결정화가 게이트 절연층에 주는 영향이 제거된 선결정화법(precrystallization)이 금속 유도 일측면 결정화(metal-induced unilateral crystallization)에 의해 제작된 다결정 실리콘 박막 트랜지스터 소자 및 회로의 전기적 특성에 미치는 영향에 대하여 연구하였다. 이 방법으로 만들어진 소자는 일반적인 후 결정화(postcrystallization) 소자에 비하여 높은 전류 구동력을 보였다. 여기에 본 연구는 DC bias에 의한 ring oscillator의 특성 변화를 연구하였다. 선결정화된 실리콘 박막을 이용하여 제작한 PMOS inverter는 후결정화된 실리콘 박막을 이용하여 제작한 inverter에 비하여 매우 동적(dynamic)이고도 안정적인 특성을 보였다.

• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.1-4
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• 2008

The electrical characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) crystallized by excimer laser annealing (ELA) method were evaluated, The polycrystalline silicon thin-film transistor (poly-Si TFT) has higher electric field-effect-mobility and larger drivability than the amorphous silicon TFT. However, to poly-Si TFT's using conventional processes, the temperature must be very high. For this reason, an amorphous silicon film on a buried oxide was crystallized by annealing with a KrF excimer laser (248 nm)to fabricate a poly-Si film at low temperature. Then, High permittivity $HfO_2$ of 20 nm as the gate-insulator was deposited by atomic layer deposition (ALD) to low temperature process. In addition, the solid phase crystallization (SPC) was compared to the ELA method as a crystallization technique of amorphous-silicon film. As a result, the crystallinity and surface roughness of poly-Si crystallized by ELA method was superior to the SPC method. Also, we obtained excellent device characteristics from the Poly-Si TFT fabricated by the ELA crystallization method.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.749-751
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• 2007

A buffer layer consisting of $SiO_x/Ta/Ti$ has been developed in order to overcome the adhesion and stress problems between poly-Si film and mica. Polycrystalline silicon thin film transistor was successfully fabricated on the mica and transferred to a flexible plastic substrate.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1292-1294
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• 1993

This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as $5{\times}10^7$.