• Journal of the Korean Society for Precision Engineering
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• v.12 no.6
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• pp.20-26
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• 1995

With the recent development of light and high efficient automobiles and aircraft, demand of the A1-Si alloy is rapidly increasing. However, there is an inclination that as the content of silicon increases it becomes more difficult to machine. Accordingly, the present study intends to analyse and study the cutting resistance and surface roughness of A1-Si alloy with Si contents of 8%, 12%, 17%, and 20%. The A1-Si alloy specimens were turned by a poly- crystalline diamond tool under selected cutting conditions, and results are here described and discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.214-215
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• 2009

This paper presents the fabrication and characteristics of microheaters, built on AlN(0.1 um)/3C-SiC(1 um) suspended membranes. Pt was used as microheater and temperature sensor materials. The results of simulated are shown that AlN/3C-SiC membrane has more large uniform-temperature area than $SiO_2$/3C-SiC membrane. Resistance of temperature sensor and power consumption of microheater were measured and calculated. Pt microheater generates the heat of about $550^{\circ}C$ at 340 mW and TCR of Pt temperature sensor is about 3188 ppm/$^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.237-237
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• 2009

Zinc oxide (ZnO) thin film was deposited on Si substrates using polycrystalline (poly) 3C-SiC buffer layer, in which the ZnO film was grown by sol-gel method. Physical characteristics of the grown ZnO film was investigated experimentally by means of SEM, XRD, FT-IR (Furier Transform-Infrared spectrum), and AFM. XRD pattern was proved that the grown ZnO film on 3C-SiC layers had highly (002) orientation with low FWHM (Full width of half maxium). These results showed that ZnO thin film grown on 3C-SiC buffer layers can be used for various piezoelectric fields and M/NEMS applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.27-27
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• 2010

This paper describes the electrical and optical characteristics of $N_2$ doped porous 3C-SiC films. Average pore diameter is about 30 nm and etched area was increased with $N_2$ doping rate. The mobility was dramatically decreased in porous 3C-SiC. The band gaps of polycrystalline 3C-SiC films and doped porous 3C-SiC were 2.5 eV and 2.7 eV, respectively.

• Electrical & Electronic Materials
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• v.10 no.8
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• pp.794-799
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• 1997

Poly-Si films have been prepared by solid phase crystallization of LPCVD(low-pressure CVD) amorphous silicon. The crystallinity of poly-Si films has been derived from UV reflectance spectrum and lies in the range between 70% and 80% . From XRD measurement the peak at 28.2$^{\circ}$from (111) plane is dominantly detected in the SPC poly-Si films, The average grain size of poly-Si film is determined by the image of SEM and varies from 4000 $\AA$ to 8000$\AA$. The electrical conductivity of as-deposited amorphous silicon film is about 2.5$\times$10$^{-7}$ ($\Omega$.cm)$^{-1}$ , and 3~4$\times$10$^{-6}$ ($\Omega$.cm)$^{-1}$ of room temperature conductivity is the SPC poly-Si films. The conductivity activation energies are 0.5~0.6 eV or the 500$\AA$-thick poly-Si films.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.6
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• pp.462-465
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• 2009

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method, The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than 10), Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• Journal of the Korean Ceramic Society
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• v.35 no.4
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• pp.333-338
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• 1998

Mechanical properties of polycrystalline{{{{ {Ti }_{3 }{SiC}_{2 } }} were investigated. Hertzian indentation test using a spher-ical indenter was used to study elastic and plastic behavior in{{{{ {Ti }_{3 }{SiC}_{2 } }} A high ratio of hardness to elastic mo-dulus indicated that mechanical properties of{{{{ {Ti }_{3 }{SiC}_{2 } }} are somehow similar to those of metals. Indentation stress-strain curve deviated from an ideal elastic limit indicating exceptional plasticity in this material. De-formation zones were formed below the contact as well as around the contact area. Intragrain slip would ac-count for high plasticity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.964-967
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• 2002

The effectiveness of silicon nitride SiNx surface passivation is investigated and quantified. This study adopted single-layer antireflection (SLAR) coating of SiNx for efficiency improvement of solar cell. The silicon nitride films were deposited by means of plasma enhanced chemical vapor deposition (PECVD) in planar coil reactor. The process gases used were pure ammonia and a mixture of silane and helium. The thickness and the refractive index on the films were measured by ellipsometry and chemical bonds were determined by using an FT-IR equipment. This films obtained were analyzed in term of hydrogen content, refractive index for gas flow ratio $(NH_3/SiH_4)$, and efficiency of solar cell. The polycrystalline silicon solar cells passivated by silicon nitride shows efficiency above 12.8%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.36-39
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• 2002

Polycrystalline silicon (poly-Si) thin film transistor (TFT) technology is emerging as a key technology for active matrix liquid crystal displays (AMLCD), allowing the integration of both active matrix and driving circuit on the same substrate (normally glass). As high temperature process is not used for glass substrate because of the low softening points below 450$^{\circ}C$. However, high temperature process is required for getting high crystallization volume fraction (i.e. crystallinity). A poly-Si thin film transistor has been fabricated to investigate the effect of high temperature process on the molybdenum (Mo) substrate. Improve of the crystallinity over 75% has been noticed. The properties of structural and electrical at high temperature poly-Si thin film transistor on Mo substrate have been also analyzed using a sputtering method

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.126-132
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• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.