• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.445-446
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• 2005

This letter reports the fabrication of polycrystalline silicon thin-film transistors (poly-Si TFT) on flexible plastic substrates using amorphous silicon (a-Si) precursor films by sputter deposition. The a-Si films were deposited with mixture gas of argon and helium to minimize the argon incorporation into the film. The precursor films were then laser crystallized using XeCl excimer laser irradiation and a four-mask-processed poly-Si TFTs were fabricated with fully self-aligned top gate structure.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2001년도 추계학술발표회 초록집
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• pp.68-68
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• 2001

Thin films of polycrystalline silicon (poly-Si) is a promising material for use in large-area electronic devices. Especially, the poly-Si can be used in high resolution and integrated active-matrix liquid-crystal displays (AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs) because of its high mobility compared to hydrogenated _amorphous silicon (a-Si:H). A number of techniques have been proposed during the past several years to achieve poly-Si on large-area glass substrate. However, the conventional method for fabrication of poly-Si could not apply for glass instead of wafer or quartz substrate. Because the conventional method, low pressure chemical vapor deposition (LPCVD) has a high deposition temperature ($600^{\circ}C-1000^{\circ}C$) and solid phase crystallization (SPC) has a high annealing temperature ($600^{\circ}C-700^{\circ}C$). And also these are required time-consuming processes, which are too long to prevent the thermal damage of corning glass such as bending and fracture. The deposition of silicon thin films on low-cost foreign substrates has recently become a major objective in the search for processes having energy consumption and reaching a better cost evaluation. Hence, combining inexpensive deposition techniques with the growth of crystalline silicon seems to be a straightforward way of ensuring reduced production costs of large-area electronic devices. We have deposited crystalline poly-Si thin films on soda -lime glass and SiOz glass substrate as deposited by PVD at low substrate temperature using high power, magnetron sputtering method. The epitaxial orientation, microstructual characteristics and surface properties of the films were analyzed by TEM, XRD, and AFM. For the electrical characterization of these films, its properties were obtained from the Hall effect measurement by the Van der Pauw measurement.

• ETRI Journal
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• 제29권1호
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• pp.45-49
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• 2007

The poly-Si thin film transistor (TFT) shows large variations in its characteristics due to the grain boundary of poly-crystalline silicon. This results in unacceptably large input offset of low-voltage differential signaling (LVDS) receivers. To cancel the large input offset of poly-Si TFT LVDS receivers, a full-digital offset compensation scheme has been developed and verified to be able to keep the input offset under 15 mV which is sufficiently small for LVDS signal receiving.

• Transactions on Electrical and Electronic Materials
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• 제6권2호
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• pp.57-62
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• 2005

Using intense pulsed ion beam evaporation technique, we have succeeded in the preparation of poly crystalline silicon thin films without impurities on silicon substrate. Good crystallinity and high deposition rate have been achieved without heating the substrate by using lEE. The crystallinity of poly-Si film has been improved with the high density of the ablation plasma. The intense diffraction peaks of poly-Si thin films could be obtained by using the substrate bias system. The crystallinity and the deposition rate of poly-Si thin films were increased by applying (-) bias voltage for the substrate.

• 한국결정성장학회지
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• 제12권3호
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• pp.120-125
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• 2002

Si-wafers for solar cells were cast in a size of $50{\times}46{\times}0.5{\textrm}{mm}^3$ by vacuum casting method. The graphite mold coated by BN powder, which was to prevent the reaction of carbon with the molten silicon, was used. Without coating, the wetting and reaction of Si melt to graphite mold was very severe. In the case of BN coating, SiC was formed in the shape of tiny islands at the surface of Si wafer by the reaction between Si-melt and carbon of the graphite mold on the high temperature. The grain size was about 1 mm. The efficiency of Si solar cell was lower than that of Si solar cell fabricated on commercial single and poly crystalline Si wafer. The reason of low efficiency was discussed.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.129-134
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• 2004

The development of fabrication processes of polycrystalline-silicon-thin-film transistors (poly-Si TFTs) at low temperatures is reviewed. Rapid crystallization through laser-induced melt-regrowth has an advantage of formation of crystalline silicon films at a low thermal budget. Solid phase crystallization techniques have also been improved for low temperature processing. Passivation of $SiO_2$/Si interface and grain boundaries is important to achieve high carrier transport properties. Oxygen plasma and $H_2O$ vapor heat treatments are proposed for effective reduction of the density of defect states. TFTs with high performance is reported.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권5호
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• pp.396-401
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• 1999

In this study, $Ar^+$ ion laser etching process of single/poly-crystalline Si with $CCl_2F_2$ gas is investigated for MEMS applications. In general, laser direct etching process is useful in microelectronic process, fabrication of micro sensors and actuators, rapid prototyping, and complementary processing because of the advantages of 3D micromachining, local etching/deposition process, and maskless process with high resolution. In this study, a pyrolytic method, in which $CCl_2F_2$ gasetches molten Si by the focused laser, was used. In order to analyze the temperature profile of Si by the focused laser, the 3D heat conduction equation was analytically solved. In order to investigate the process parameters dependence of etching characteristics, laser power, $CCl_2F_2$ gas pressure, and scanning speed were varied and the experimental results were observed by SEM. The aspect ratio was measured in multiple scanning and the simple 3D structure was fabricated. In addition, the etching characteristics of $6\mum$ thick poly-crystalline Si on the insulator was investigated to obtain flat bottom and vertical side wall for MEMS applications.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.322-325
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• 2000

N-channel poly-Si TFT, Processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after electrical stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5$\mu\textrm{m}$ and 3$\mu\textrm{m}$ poly-Si TFTs are 3.3V, 3.V respectively. With the threshold voltage shia the degradation of transconductance(G$\_$m/) and subthreshold swing(S) is also observed.

• 한국결정성장학회지
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• 제20권6호
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• pp.254-261
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• 2010

본 연구에서는 다결정 실리콘 태양전지 응용을 위한 다결정 실리콘 씨앗층의 제조와 그의 특성에 관한 연구를 수행하였다. 다결정 실리콘 씨앗층은 glass/Al/$Al_2O_3$/a-Si 구조를 이용하여 aluminum-induced layer exchange(ALILE) 고정으로 제조하였으며, 자연산화막부터 50 nm까지 다양한 크기로 $Al_2O_3$ 막두께를 변화시켜 알루미늄 유도 결정화 공정에서 막의 두께가 결정화 특성 및 결정결함, 결정크기에 미치는 영향에 대하여 조사하였다. 연구결과, ALILE 공정으로 생성된 다결정 실리콘막의 결함은 $Al_2O_3$ 막의 두께가 증가할수록 함께 증가한 반면, 결정화 정도와 결정입자의 크기는 $Al_2O_3$막의 두께가 증가할수록 감소하였다. 본 실험에서는 16 nm 두께 이하의 앓은 $Al_2O_3$ 막의 구조에서 평균 약 $10\;{\mu}m$ 크기의 sub-grain 결정립을 얻었으며, 결정성은 <111> 방향의 우선 배향성 특성을 보였다.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.364-369
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• 2011

Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by $7.1{\times}10^1$. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.