• 전자공학회논문지A
• /
• 제32A권8호
• /
• pp.126-132
• /
• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• ETRI Journal
• /
• 제35권3호
• /
• pp.425-430
• /
• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제50권10호
• /
• pp.489-493
• /
• 2001

The on-current of offset and LDD structured devices in slightly decreased while the off-current are remarkably reduced and almost constant independent of gate and drain voltage because offset and LDD regions behave as a series resistance and reduce the lateral electric field in the drain depletion. Degradation of these devices is dependent upon the offset and LDD length rather than doping concentration in these regions. Also, degradation mechanism has been related to the interface generation rather than the hot carrier injection into gate oxide.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2000년도 하계학술대회 논문집 C
• /
• pp.1751-1753
• /
• 2000

다결정 실리콘 박막 트랜지스터 (poly-Si TFT)의 누설전류를 억제하기 위해 게이트 절연막(gate oxide)의 가장자리에 캐비티(cavity)를 가지는 새로운 구조의 다결정 박막 트랜지스터를 제안하였다. 캐비티는 드레인(drain) 공핍영역(depletion region) 위에 형성되어 드레인 주변에 유도되는 수직전계를 감소시켜 누설전류를 억제하고 소자의 안정성을 향상시킬 수 있다. 본 연구에서 제작된 poly-Si TFT는 기존의 TFT에 비해 온-오프 전류비가 향상되었고 전기적 스트레스 후의 문턱전압 변화가 작음을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
• /
• pp.153-154
• /
• 2000

Large size poly-Si TFT-LCDs have been fabricated using p-channel thin film transistors for notebook PC application. We have designed and implemented the data sampling circuit and gate drivers that operate with low power consumption and high reliability. The gate driver has a redundant structure. We have realized the uniform and excellent display quality comparable to that of CMOS module. The reliability of panel is investigated and discussed by measuring the bias stability of transistors.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.225-228
• /
• 2001

We simulated and analyzed the flicker phenomena in the poly-Si TFT-LCD using PSpice for the development of wide-area and high-quality LCD display We define the electric quantity of flicker in the TFT-LCD, which is the ratio of half frame frequency (30Hz) to DC (0 Hz) frequency. We compared two different types of TFTs, excimer laser annealed (ELA) poly-Si TFT and silicide mediated crystallization (SMC) poly-Si TFT, and found that the ELA and SMC TFTs show different flicker characteristics because of their mobility and leakage current. In addition, we showed that the gate voltage should be chosen carefully at the minimum flicker because of the larger leakage current of poly-Si Tn as compared with a-Si TFT

• 한국전기전자재료학회논문지
• /
• 제14권11호
• /
• pp.869-873
• /
• 2001

The effects of alternate bias stress on p-channel poly-Si TFT\`s has been systematically investigated. We alternately applied positive and negative bias stress on p-channel poly-Si TFT\`s, device Performance(V$\_$th/, g$\_$m/, leakage current, S-slope) are alternately appeared to be increasing and decreasing. It has been shown that device performance degrade under the negative bias stress while improve under the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ interface under alternate bias stress.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 1996년도 제10회 학술발표회 논문개요집
• /
• pp.40-40
• /
• 1996

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 추계학술대회 논문집
• /
• pp.60-61
• /
• 2007

In this paper, the p-channel poly Si thin-film transistors (Poly-Si TFT's) using formed by solid phase crystallization (SPC) on glass substrate were fabricated. And we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's to indicate non-volatile memory (NVM) effect. Poly-Si TFT is investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, on/off current ratio. NVM characteristics is showed by measuring the threshold voltage change of TFT through I-V characteristics.

• 한국재료학회지
• /
• 제15권5호
• /
• pp.301-305
• /
• 2005

We fabricated nickel silicide layers on whole non-patterned wafers from $p-Si(100)SiO_2(200nm)$/poly-Si(70 nm)mn(40 nm) structure by 40 sec rapid thermal annealing of $500\~900^{\circ}C$. The sheet resistance, cross-sectional microstructure, surface roughness, and phase analysis were investigated by a four point probe, a field emission scanning electron microscope, a scanning probe microscope, and an X-ray diffractometer, respectively. Sheet resistance was as small as $7\Omega/sq$. even at the elevated temperature of $900^{\circ}C$. The silicide thickness and surface roughness increased as silicidation temperature increased. We confirmed the nickel silicides iron thin nickel/poly-silicon structures would be a mixture of NiSi and $NiSi_2$ even at the $NiSi_2$ stable temperature region.