• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.673-674
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• 2003

The reliability of TFT, crystallized by sequential lateral solidification (SLS) technology, has been studied High current damage is characterized by high gate bias (-20V) and drain bias (-10V). It is found that performance of SLS TFTs is enhanced by high current stress up to 300 sec of stress time for 20/8 (W/L) N-TFT. After that, TFT performance is degraded with the increase of the stress time. It is speculated from the experimental data that SLS TFTs initially contain a number of unstable defect states. Then, the defect states seem to be cured by high current stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.345-345
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• 2010

1T-DRAM cell with solid phase (SPC) crystallized poly-Si thin film transistor was fabricated and electrical characteristics were evaluated. The fabricated device showed kink effect by negative back bias. Kink current is due to the floating body effect and it can be used to memory operation. Current difference between "1" state and "0" state was defined and the memory properties can be improved by using gate induced drain leakage (GIDL) current.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.2014-2016
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• 2002

Liquid crystal displays(LCDs)의 스위칭 소자로써 thin film transistors(TFTs)를 적용하기 위해서 저온 공정이 가능하도록 molybdenum 금속을 게이트에 사용하여 저온 다결정 TFTs 소자를 제작하였다. 또한, 채널 길이 방향으로 결정을 성장시켜 결정립이 큰 다결정 실리콘을 얻을 수 있는 sequential lateral solidification(SLS) 결정화 방법을 사용하였다. SLS-TFT 소자를 $2{\mu}m$에서 $20{\mu}m$까지의 다양한 채널 길이와 폭으로 제작한 후 각 소자들의 I-V 특성 곡선과 소자의 물성 분석을 위해 필요한 변수들을 구하여 이들의 전기적인 특성을 비교, 분석하였다. 제작된 소자들로부터 측정된 이동도는 $100{\sim}400Cm^2$/Vs, on/off 전류비는 약 $10^7$, off-state 전류는 약 $100{\times}10^{-12}A$로 대체적으로 우수한 특성을 보였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.409-412
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• 2007

A lot of research for system-on-panel(SOP) have been done to integrate display systems including data driver, gate driver, timing controller, DC-DC converter, and smart functions such as embedded touch screen, ambient brightness sensing and luminance control, finger printing on the glass. Recently, the cost of an one-chip driver IC with various functions has decreased rapidly, and new mobile display interface technologies have been introduced. So it is necessary to examine the feasibility of SOP for practical mobile applications. In this paper, we will re-examine LTPS technologies for mobile displays in terms of various aspects and discuss the practical limitations on SOP technology and future technology trend of mobile displays.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.151-151
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• 2010

In this paper, the electrically properties of nonvolatile memory (NVM) using multi-stacks gate insulators of oxide-nitride-oxynitride (ONOn) and active layer of the low temperature polycrystalline silicon (LTPS) were investigated. From hydrogenated amorphous silicon (a-Si:H), the LTPS thin films with high crystalline fraction of 96% and low surface's roughness of 1.28 nm were fabricated by the metal induced crystallization (MIC) with annealing conditions of $650^{\circ}C$ for 5 hours on glass substrates. The LTPS thin film transistor (TFT) or the NVM obtains a field effect mobility of ($\mu_{FE}$) $10\;cm^2/V{\cdot}s$, threshold voltage ($V_{TH}$) of -3.5V. The results demonstrated that the NVM has a memory window of 1.6 V with a programming and erasing (P/E) voltage of -14 V and 14 V in 1 ms. Moreover, retention properties of the memory was determined exceed 80% after 10 years. Therefore, the LTPS fabricated by the MIC became a potential material for NVM application which employed for the system integration of the panel display.

• Applied Science and Convergence Technology
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• v.24 no.3
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• pp.53-59
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• 2015

The field-effect transistors (FETs) with a graphene-based p-n junction channel were fabricated using the patterned self-assembled monolayers (SAMs). The self-assembled 3-aminopropyltriethoxysilane (APTES) monolayer deposited on $SiO_2$/Si substrate was patterned by hydrogen plasma using selective coating poly-methylmethacrylate (PMMA) as mask. The APTES-SAMS on the $SiO_2$ surface were patterned using selective coating of PMMA. The APTES-SAMs of the region uncovered with PMMA was removed by hydrogen plasma. The graphene synthesized by thermal chemical vapor deposition was transferred onto the patterned APTES-SAM/$SiO_2$ substrate. Both p-type and n-type graphene on the patterned SAM/$SiO_2$ substrate were fabricated. The graphene-based p-n junction was studied using Raman spectroscopy and X-ray photoelectron spectroscopy. To implement low voltage operation device, via ionic liquid ($BmimPF_6$) gate dielectric material, graphene-based p-n junction field effect transistors was fabricated, showing two significant separated Dirac points as a signature for formation of a p-n junction in the graphene channel.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.379-379
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• 2013

본 논문에서는 Normal ink jetting 공법으로 OTFT를 제작할 때 coffee stain effect에 의해서 반도체 소자의 특성이 저하되는 것을 극복하기 위해서 동일한 위치에 동일한 부피로 Droplet을 형성하는 Multiple ink jetting 공법을 통해 TIPS pentacene 결정의 Morphology와 전기적 특성이 어떻게 변화하는지 알아 보았다. Multiple ink jetting의 drop 횟수가 증가할수록 coffee stain effect에 의해서 형성된 가운데 영역의 Dendrite grain이 점점 작아지다가 7 Drops 이후로는 Big grain 만 남게 되었다. Active layer의 표면 Roughness는 drop 횟수가 증가할수록 낮아지다가 일정 count 이후로는 다시 높아지는 것을 확인할 수 있었다. 전계 이동도(mobility)는 drop 횟수가 증가할수록 커지다가 일정 count 이후로는 saturation되는 것을 확인할 수 있었다. Multiple ink jetting에 의해서 만들어진 OTFT 소자의 전계 이동도(mobility)는 1 drop과 10 drops에서 각각 0.0059, 0.036 cm2/Vs 로 6배 정도 차이가 있었다. 이것은 첫 drop에 의해 만들어진 가운데 Dendrite grain 영역이 Multiple ink jetting을 반복하면서 점점 작아지게 되어 사라지고 두꺼운 Grain 영역만 남게 된 것으로 판단된다. Vth 와 On/Off ratio는 1 drop과 10 drops에서 각각 -3 V, -2 V 그리고 $3.3{\times}10^3$, $1.0{\times}10^4$를 보였다. OTFT의 substrate로 Flexible한 polyethersulfone (PES) 기판을 사용하였고, 절연체로 Spin coating된 Poly-4-vinylphenol (PVP)가 사용되었으며, Gate 및 Source/Drain 전극은 Au를 50 nm 두께로 증착하였다. Channel의 width와 length는 각각 100 um, 40 um 였고, Gate 전극 위에 Active layer를 형성한 Bottom gate 구조로 제작되었다. Ink jet으로 제작된 TIPS pentacene의 결정성은 x-ray diffraction (XRD)와 광학 현미경으로 분석하였고 Thickness profile은 알파스텝 측정기를 이용하였으며, OTFT의 전기적 특성은 Keithley-4,200을 사용하여 측정하였다.

• Journal of the Korean Applied Science and Technology
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• v.27 no.2
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• pp.137-143
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• 2010

Oxide semiconductors Thin-film transistors are an exemplified one owing to its excellent ambient stability and optical transparency. In particular zinc oxide (ZnO) has been reported because It has stability in air, a high electron mobility, transparency and low light sensitivity, compared to any other materials. For this reasons, ZnO TFTs have been studied actively. Furthermore, we expected that would be satisfy the demands of flexible display in new generation. In order to do that, ZnO TFTs must be fabricated that flexible substrate can sustain operating temperature. So, In this paper we have studied low-temperature process of zinc oxide(ZnO) thin-film transistors (TFTs) based on silicon nitride ($SiN_x$)/cross-linked poly-vinylphenol (C-PVP) as gate dielectric. TFTs based on oxide fabricated by Low-temperature process were similar to electrical characteristics in comparison to conventional TFTs. These results were in comparison to device with $SiN_x$/low-temperature C-PVP or $SiN_x$/conventional C-PVP. The ZnO TFTs fabricated by low-temperature process exhibited a field-effect mobility of $0.205\;cm^2/Vs$, a thresholdvoltage of 13.56 V and an on/off ratio of $5.73{\times}10^6$. As a result, We applied experimental for flexible PET substrate and showed that can be used to ZnO TFTs for flexible application.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.111-121
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• 2012

In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

• Advances in Energy Research
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• v.1 no.2
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• pp.97-106
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• 2013

This study designs and tests a photovoltaic system with distributed maximum power point tracking (DMPPT) methodology using a field programmable gate array (FPGA) controller. Each solar panel in the distributed PV system is equipped with a newly designed DC/DC converter and the panel's voltage output is regulated by a FPGA controller using PI control. Power from each solar panel on the system is optimized by another controller where the quadratic maximization MPPT algorithm is used to ensure the panel's output power is always maximized. Experiments are carried out at atmospheric insolation with partial shading conditions using 4 amorphous silicon thin film solar panels of 2 different grades fabricated by Chi-Mei Energy. It is found that distributed MPPT requires only 100ms to find the maximum power point of the system. Compared with the traditional centralized PV (CPV) system, the distributed PV (DPV) system harvests more than 4% of solar energy in atmospheric weather condition, and 22% in average under 19% partial shading of one solar panel in the system. Test results for a 1.84 kW rated system composed by 8 poly-Si PV panels using another DC/DC converter design also confirm that the proposed system can be easily implemented into a larger PV power system. Additionally, the use of NI sbRIO-9642 FPGA-based controller is capable of controlling over 16 sets of PV modules, and a number of controllers can cooperate via the network if needed.