• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.23-30
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• 1993

Hydrogenation on the top gate and bottom gate Poly-Si TET's was performed by using Nh$_{3}$ plasma and annealing SiN film deposited by PECVD and then the electric characteristics on Poly-Si TET were investigated. As the time of NA$_{3}$ plasma treatment increaes, on/off current ratio gradually increases and the swing value decreases. The trap densities of graim boundaries in Poly-Si decrease very much during the inital 20min of hydrogenation time, and the decreasing scale becomes smaller after 20 min. The electric characteristics of the top gate TFT are better than those of the bottom gate TFT, it is considered due to the defects at the interface between the Poly-Si and the underlayer, SiO$_{2}$. After NH$_{3}$ plasma was treated for 2 hours for the top gate TFT, as the aging time atroon temperature increases on current was not scacely changed and off current decreases more than 1 order. Gate current density recovers to original value after the aging treatment for 8 days and then the electric characteristics are finally improved. It is suggested that the degraded characteristics of gate oxide are improved, from the variations of C-V characteristics with aging time. For the hydrogenation of isothermal and isochronal annealing SiN film deposited by PECVD, the characteristics of Poly-Si TFT are improved with increasing annealing temperature and are not largely changed with increasing annealing time. This results is good in agreement with the hydrogen reduction in Sin film as variations of annealing temperature and time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12
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• pp.1065-1070
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• 2003

HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.127-133
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• 1996

In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photoresist reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate form both sides of the main gate. The poly-Si channel layer below the offset oxide is protected form the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of oru new device is the offset region due to the offset oxide. our experimental reuslts show that the offset region, due to the photoresist reflow process, has been sucessfully obtained in order to fabricate the offset gated poly-Si TFTs. The maximum ON/OFF ratio occurs at the L$_{off}$ of 1.1${\mu}$m and exceeds 1X10$^{6}$.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1502-1504
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• 1996

The effects of electrical stress in hydrogen passivated and as-fabricated poly-Si TFT's are investigated. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which has been stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2031-2033
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• 2005

poly-Si TFT의 kink 전류를 억제하는 L-shaped dual-gate TFT 구조를 제안하고 이를 제작하였다. 제안된 소자는 채널의 그레인 방향을 일정하게 성장시키는 SLS나 CW laser 결정화 방법을 사용한다. L자 모양의 게이트 구조를 사용하여 서고 다른 전계효과 이동도를 갖는 두 개의 sub-TFT를 구현할 수 있으며, 이러한 sub-TFT간의 특성차이가 kink 전류를 억제시킨다. 직접 제작한 L-shaped dual-gate 구조의 소자가 poly-Si TFT의 kink 전류를 억제하고, 전류포화 영역에서 전류량을 고정시킴으로써 신뢰성이 향상됨을 확인하였다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.367-372
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• 1999

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.180-186
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• 2023

Positive bias temperature instability (PBTI) degradation of n⁺ and p⁺ poly-Si gate high-voltage(HV) SiO2 dielectric nMOSFETs was investigated. Unlike the expectation that degradation of n⁺/nMOSFET will be greater than p⁺/nMOSFET owing to the oxide electric field caused by the gate material difference, the magnitude of the PBTI degradation was greater for the p⁺/nMOSFET than for the n⁺/nMOSFET. To analyze the cause, the interface state and oxide charge were extracted for each case, respectively. Also, the carrier injection and trapping mechanism were analyzed using the carrier separation method. As a result, it has been verified that hole injection and trapping by the p⁺ poly-Si gate accelerates the degradation of p⁺/nMOSFET. The carrier injection and trapping processes of the n⁺ and p⁺ poly-Si gate high-voltage nMOSFETs in PBTI are detailed in this paper.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.90-93
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• 1996

The conduction mechanisms of the off-current in low temperature ($\leq$600$^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT's) has been systematically studied. Especially, the temperature and bias dependence of the off-current between unpassivated and passivated poly-Si TFT's was investigated and compared. The off-current of unpassivated poly-Si TFT's is due to a resistive current at low gate and drain voltage, thermal emission current at high gate, low drain voltage, and field enhanced thermal emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation, it was observed that the off-currents were remarkably reduced by plasma-hydrogenation. It was also observed that the off-currents of the passivated poly-Si TFT's are more critically dependent on temperature rather than electric field.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.315-318
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• 1999

We have proposed and fabricated the new bottom-gated polycrystalline silicon (poly-Si) thin film transistor (TFT) with a partial amorphous-Si region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the ON/OFF current ratio is increased significantly by more than three orders in the new poly-Si TFT compared with conventional poly-Si TFT. The leakage current is decreased significantly due to the highly resistive a-Si re TFTs while the ON-series resistance of the local a-Si is reduced significantly due to the considerable inducement of electron carriers by the positive gate bias, so that the ON-current is not decreased much.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1315-1317
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• 1998

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshold voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate bias stressing and under the gate and drain bias stressing. Also, we have quantitatively analized the degradation phenomena using by analytical method. we have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the poly-Si is prevalent in gate and drain bias stressed device.