• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.157-162
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• 2006

Chemical-mechanical polishing (CMP), one of the dominant technology for ULSI planarization, is used to flatten the micro electro-mechanical systems (MEMS) structures. The objective of this paper is to achieve good planarization of the deposited film and to improve deposition efficiency of subsequent layer structures by using surface-micromachining process in MEMS technology. Planarization characteristic of poly-Si film deposited on thin oxide layer with MEMS structures is evaluated with different slurries. Patterns used for this research have shapes of square, density, line, hole, pillar, and micro engine part. Advantages of CMP process for MEMS structures are observed respectively by using the test patterns with structures larger than 1 urn line width. Preliminary tests for material selectivity of poly-Si and oxide are conducted with two types of silica slurries: $ILD1300^{TM}\;and\;Nalco2371^{TM}$. And then, the experiments were conducted based on the pretest. A selectivity and pH adjustment of slurry affected largely step heights of MEMS structures. These results would be anticipated as an important bridge stone to manufacture MEMS CMP slurry.

• Transactions on Electrical and Electronic Materials
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• v.13 no.5
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• pp.237-240
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• 2012

A conducting polymer, poly 3-hexylthiophene (P3HT) is characterized with the metal-insulator-semiconductor (MIS) measurement method and the high frequency planar circuit method. From the MIS measurement method, the relative dielectric constant of the P3HT film is estimated to be 4.4. For the high frequency planar circuit method, a coplanar waveguide is fabricated on the P3HT film. When applying +20 V to the CPW on P3HT film, the P3HT film is in accumulation mode and becomes lossy. The CPW on P3HT film is 1.5 dB lossier than the CPW on $SiO_2$ film without P3HT film at 50 GHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.2
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• pp.106-110
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• 1998

The $LiNbO_3$ thin films were prepared directly on Si(100) substrates by conventional RF magnetron spurttering system for nonvolatile memory applications. RTA(Rapid Thermal Annealing) treatment was performed for as-deposited films in an oxygen atmosphere at 600 $^{\circ}C$ for 60 s. The rapid thermal annealed films were changed to poly-crystalline ferroelectric nature from amorphous of as-deposition. The resistivity of the ferroelectric $LiNbO_3$ film was increased from a typical value of $1{\sim}2{\times}10^8{\Omega}{\cdot}cm$ before the annealing to about $1{\times}10^{13}{\Omega}{\cdot}cm$ at 500 kV/cm and reduced the interface state density of the $LiNbO_3/Si$ (100) interface to about $1{\times}10^{11}/cm^2{\cdot}eV$. Ferroelectric hysteresis measurements using a Sawyer-Tower circuit yielded remanent polarization ($P_r$) and coercive field ($E_c$) values of about 1.2 ${\mu}C/cm^2$ and 120 kV/cm, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.2
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• pp.207-212
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• 2013

A novel pixel circuit that uses only n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS-TFTs) to compensate the threshold voltage variation of a OLED driving TFT is proposed. The proposed 6T1C pixel circuit consists of 5 switching TFTs, 1 OLED driving TFT and 1 capacitor. When the threshold voltage of driving TFT varies by ${\pm}0.33$ V, Smartspice simulation results show that the maximum error rate of OLED current is 7.05 % and the error rate of anode voltage of OLED is 0.07 % at Vdata = 5.75 V. Thus, the proposed 6T1C pixel circuit can realize uniform output current with high immunity to the threshold voltage variation of poly-Si TFT.

• Journal of Integrative Natural Science
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• v.5 no.4
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• pp.237-240
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• 2012

In this study, PEDOT thin films polymerized with Iron(III)tosylate ($Fe(PTS)_3$) and grown on atomically smooth and highly dense 3-aminopropyltriethoxysilane self-assembled monolayer (APS-SAM) surfaces by VPP method have been investigated. PEDOT thin films were synthesized on APS self-assembled $SiO_2$ wafer surface at two different concentrations (20 wt% and 40 wt%) and growth time (3 and 30 minutes), and then their sheet resistance were measured and compared. PEDOT thin films grown with 20 wt% $Fe(PTS)_3$ oxidant are highly conductive when compared with the film grown with 40 wt% $Fe(PTS)_3$, as ascertained by the measured sheet resistance values down to 0.06 ${\Omega}/cm$. It clearly suggests that 20 wt% is more effective oxidant concentration for VPP than 40 wt% even though the film grown with 40 wt% oxidant has better quality than the film with 20 wt% $Fe(PTS)_3$ does.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.166-171
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• 2016

Nickel silicide is main issue in Polycrystalline silicon Thin Film Transistor (TFT) which is made by Metal Induced Lateral Crystallization (MILC) method. This Nickel silicide acts as a defect center, and this defect is one of the biggest reason of the high leakage current. In this research, we fabricated polycrystalline TFTs with novel method called Edge Cut (EC). With this new fabrication method, we assumed that nickel silicide at the edge of the channel region is reduced. Electrical properties are measured and trap state density also calculated using Levinson & Proano method.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1414-1415
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• 2011

높은 게이트와 드레인 바이어스 스트레스 조건에서 신뢰성을 높이기 위해 비대칭 스페이싱 다중채널 구조 (ASS) 를 이용한 다결정 실리콘 박막 트래지스터 (poly-Si TFTs) 를 제안하였다. 이것은 어떠한 추가공정 없이 제작할 수 있고 채널 가운데 부분의 넓은 공간을 이용하여 소자안의 유도된 열을 방출할 수 있기 때문에 기존의 트랜지스터에 비해 47%의 문턱전압감소와 3%의 이동도 변화 감소를 보인다. 이 실험결과는 제안된 소자구조가 기존의 소자에 비해 높은 게이트와 드레인 바이어스 조건에서 전기적 특성이 더 안정적이라는 것을 보여준다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.233-236
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• 2000

Polycrystalline Silicon Thin Film Transistors(Poly-Si TFT's), fabricated at temperature lower than $600^{\circ}C$ are now largely used in many applications, particularly in large area electrons. In this work, electrical stress effects on Poly-Si TFT's fabricated by Solid Phase Crystal(SPC) was investigated by measuring electric properities such as transfer and output characteristics, and channel conductance. Consequently, It is turned out that it should be noted the output characteristics, drain current and channel conductance, strongly degrade around origin.

• Journal of Information Display
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• v.8 no.4
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• pp.15-18
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• 2007

In this paper, we investigated the SLS process to control grain boundary(GB) location in TFT channel region, and it has been found to be applicable for locating the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analysed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.6
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• pp.254-261
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• 2010

Polycrystalline silicon (pc-Si) films are fabricated and characterized for application to pc-Si thin film solar cells as a seed layer. The amorphous silicon films are crystallized by the aluminum-induced layer exchange (ALILE) process with a structure of glass/Al/$Al_2O_3$/a-Si using various thicknesses of $Al_2O_3$ layers. In order to investigate the effects of the oxide layer on the crystallization of the amorphous silicon films, such as the crystalline film detects and the crystal grain size, the $Al_2O_3$ layer thickness arc varied from native oxide to 50 nm. As the results, the defects of the poly crystalline films are increased with the increase of $Al_2O_3$ layer thickness, whereas the grain size and crystallinity are decreased. In this experiments, obtained the average pc-Si sub-grain size was about $10\;{\mu}m$ at relatively thin $Al_2O_3$ layer thickness (${\leq}$ 16 nm). The preferential orientation of pc-Si sub-grain was <111>.