• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.186-186
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• 2000

After LeComber et al. reported the first amorphous hydrogenated silicon (a-Si: H) TFT, many laboratories started the development of an active matrix LCDs using a-Si:H TFTs formed on glass substrate. With increasing the display area and pixel density of TFT-LCD, however, high mobility TFTs are required for pixel driver of TF-LCD in order to shorten the charging time of the pixel electrodes. The most important of these drawbacks is a-Si's electron mobiliy, which is the speed at which electrons can move through each transistor. The problem of low carier mobility for the a-Si:H TFTs can be overcome by introducing polycrystalline silicon (poly-Si) thin film instead of a-Si:H as a semiconductor layer of TFTs. Therefore, poly-Si has gained increasing interest and has been investigated by many researchers. Recnetly, fabrication of such poly-Si TFT-LCD panels with VGA pixel size and monolithic drivers has been reported, . Especially, fabricating poly-Si TFTs at a temperature mach lower than the strain point of glass is needed in order to have high mobility TFTs on large-size glass substrate, and the monolithic drivers will reduce the cost of TFT-LCDs. The conventional methods to fabricate poly-Si films are low pressure chemical vapor deposition (LPCVD0 as well as solid phase crystallization (SPC), pulsed rapid thermal annealing(PRTA), and eximer laser annealing (ELA). However, these methods have some disadvantages such as high deposition temperature over $600^{\circ}C$, small grain size (<50nm), poor crystallinity, and high grain boundary states. Therefore the low temperature and large area processes using a cheap glass substrate are impossible because of high temperature process. In this study, therefore, we have deposited poly-Si thin films on si(100) and glass substrates at growth temperature of below 40$0^{\circ}C$ using newly developed high rate magnetron sputtering method. To improve the sputtering yield and the growth rate, a high power (10~30 W/cm2) sputtering source with unbalanced magnetron and Si ion extraction grid was designed and constructed based on the results of computer simulation. The maximum deposition rate could be reached to be 0.35$\mu$m/min due to a high ion bombardment. This is 5 times higher than that of conventional sputtering method, and the sputtering yield was also increased up to 80%. The best film was obtained on Si(100) using Si ion extraction grid under 9.0$\times$10-3Torr of working pressure and 11 W/cm2 of the target power density. The electron mobility of the poly-si film grown on Si(100) at 40$0^{\circ}C$ with ion extraction grid shows 96 cm2/V sec. During sputtering, moreover, the characteristics of si source were also analyzed with in situ Langmuir probe method and optical emission spectroscopy.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권10호
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• pp.489-493
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• 2001

The on-current of offset and LDD structured devices in slightly decreased while the off-current are remarkably reduced and almost constant independent of gate and drain voltage because offset and LDD regions behave as a series resistance and reduce the lateral electric field in the drain depletion. Degradation of these devices is dependent upon the offset and LDD length rather than doping concentration in these regions. Also, degradation mechanism has been related to the interface generation rather than the hot carrier injection into gate oxide.

• 한국진공학회지
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• 제12권2호
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• pp.130-135
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• 2003

최근, poly-Si 박막은 저가의 박막소자응용을 위하여 사용되어 왔다. 그러나, 유리기판 위에서 일반적인 고상결정화(SPC) 방식으로 poly-Si 박막을 얻기는 불가능하다. 이러한 단점 때문에 유리와 같은 저가기판 위에 poly-Si을 결정화하는 연구가 최근 다양하게 진행되고 있다. 본 논문에서는 급속열처리(RTA)를 이용하여 유연한 기판인 몰리브덴 기판 위에서 a-Si:H를 성장시킨 후 고온결정화에 대한 연구를 진행하였다 고온결정화된 poly-Si 박막은 150$\mu\textrm{m}$ 두께의 몰리브덴 기판 위에 성장되었으며 결정화 온도는 고 진공하에서 $750^{\circ}C$~$1050^{\circ}C$ 사이에서 결정화된 시료에 대하여 결정화도, 결정화 면방향, 표면구조 및 전기적 특성이 조사되었다. 결정화온도 $1050^{\circ}C$에서 3분간 결정화된 시료의 결정화도는 92%를 나타내고 있었다. 결정화된 poly-Si 박막으로 제작된 TFT 소자로부터 전계효과 이동도 67 $\textrm{cm}^2$/Vs을 얻을 수 있었다.

• 센서학회지
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• 제6권6호
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• pp.483-490
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• 1997

Thin film Si has been used in sensors, radiation detectors, and solar cells. The carrier mobility of thin film Si influences the device behavior through its frequency response or time response. Since poly-Si shows the higher mobility value, a-Si:H films on Mo substrate were subjected to various crystallization treatments. Consequently, we need to find an appropriate method in mobility measurement before and after the anneal treatment. This paper investigates the carrier mobility improvement with anneal treatments and summarizes the mobility measurement methods of the a-Si:H and poly-Si film. Various techniques were investigated for the mobility determination such as Hall mobility, HS, TOF, SCLC, TFT, and TCO method. We learned that TFT and TCO method are suitable for the mobility determination of a-Si:H and poly-Si film. The measured mobility was improved by $2{\sim}3$ orders after high temperature anneal above $700^{\circ}C$ and grain boundary passivation using an RF plasma rehydrogenation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.128-128
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• 2011

Polysilicon thin-film transistors (poly-Si TFTs)는 능동행렬 액정 표시 소자(AMLCD : Active Matrix Liquid Crystal Display)와 DRAM과 같은 메모리 분야에 폭넓게 적용이 가능하기 때문에 많은 연구가 진행되고 있다. 최근 poly-Si TFTs의 우수한 특성으로 인하여 주변 driving circuits에 직접화가 가능하게 되었다. 또한 디스플레이 LCD 패널에 controller와 메모리와 같은 다 기능의 장치을 직접화 하여 비용의 절감과 소자의 소형화가 가능한 SOP (System on panels)에 연구 또한 진행 되고 있다. 이미 잘 알려진 바와 같이 비휘발성 메모리는 낮은 소비전력과 비휘발성이라는 특성 때문에 이동식 디바이스에 데이터 저장 장치로 많이 사용되고 있다. 하지만 플로팅 타입의 비휘발성 메모리는 제작공정의 문제로 인하여 SOP의 적용에 어려움을 가지고 있다. SONOS 타입의 메모리는 빠른 쓰기/지우기 효율과 긴 데이터 유지 특성을 가지고 있으나 소자의 스케일링 따른 누설전류의 증가와 10년의 데이터 보존 특성을 만족 시킬 수 가 없는 문제가 발생한다. 본 연구에서는 SOP 적용을 위하여 ELA 방법을 통하여 결정화한 poly-Si TFT memory를 SiO2/Si3N4/SiO2 Tunnel barrier와 High-k HfO2과 Al2O3을 Trapping layer와 Blocking layer로 적용, 비휘발성 메모리을 제작하여 전기적 특성을 알아보았다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 영호남학술대회 논문집
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• pp.233-236
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• 2000

Polycrystalline Silicon Thin Film Transistors(Poly-Si TFT's), fabricated at temperature lower than $600^{\circ}C$ are now largely used in many applications, particularly in large area electrons. In this work, electrical stress effects on Poly-Si TFT's fabricated by Solid Phase Crystal(SPC) was investigated by measuring electric properities such as transfer and output characteristics, and channel conductance. Consequently, It is turned out that it should be noted the output characteristics, drain current and channel conductance, strongly degrade around origin.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.266-269
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• 1997

Hot carrier effects as a function of bias stress time and bias stress conditions were syste-matica1ly investigated in p-channel po1y-Si TFT's fabricated on the quartz substrate. The device degradation was observed for the negative bias stress. After positive bias stressing, Improvement of electrical characteristic except for subthreshold slope was observed. It was found that these results were related to the hot carrier injection into the gate oxide and interface states at the poly-Si/SiO$_2$interface rather than defects states generation under bias stress.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.297-300
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• 2005

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) fabricated using sputter deposited amorphous silicon (a-Si) precursor films are investigated. The a-Si films were deposited on flexible polymer substrates using argon-helium mixture gases to minimize the argon incorporation into the film. The precursor films were then laser annealed by using a XeCl excimer laser and a four-mask-processed poly-Si TFT was fabricated with fully self-aligned top gate structure. The fabricated pMOS TFT showed field-effect mobility of $32.4cm^2/V{\cdot}s$ and on/off ratio of $10^6$.

• 마이크로전자및패키징학회지
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• 제24권3호
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• pp.7-11
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• 2017

본 논문은 3차원 낸드 플래쉬 기억 소자에 적용을 위해 소노스(SONOS) 형태로 기억 저장 절연막을 채용하고 채널로 폴리실리콘을 사용한 박막형 트랜지스터에 대해 연구하였다. 셀의 source/drain에는 불순물을 주입 하지 않았고, 셀 양 끝단에는 선택 트랜지스터를 배치하였다. 셀의 채널과 선택 트랜지스터의 source/drain 불순물 농도 변화에 대한 평가를 진행하여 공정 최적화를 하였다. 선택 트랜지스터의 농도 증가 시 채널 전류의 상승 및 삭제특성이 개선됨을 확인 하였는데 이는 GIDL에 의한 홀 생성이 증가하였기 때문이다. 최적화된 공정 변수에 대해 삭제와 쓰기 후 문턱전압의 프로그램 윈도우는 대략 2.5V를 얻었다. 터널 산화막 공정 온도에 대한 평가 결과 온도 증가 시 swing 및 신뢰성 항목인 bake 결과가 개선됨을 확인하였다.

• 한국전기전자재료학회논문지
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• 제11권10호
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• pp.918-923
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• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.