• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1266-1269
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• 2007

Polycrystalline silicon (poly-Si) films were prepared directly on plastic substrates at a low (< $200^{\circ}C$) by using Catalytic Chemical Vapor Deposition (Cat-CVD) technique without subsequent annealing steps. Surface roughness of the poly-Si layer and the density of the gate dielectric layer were found to be influential to the TFT performance.

• 한국재료학회지
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• 제5권2호
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• pp.203-207
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• 1995

Polysilicon this film transistors (poly-Si TFTs) with different channel dimensions were fabricated on low-temperature crystalized amorphous silicon films and on as-deposited polysilicon films. The electrical characteristics of these TFTs were characterized and compared. The performance of the TFTs fabricated on the solid-phase crystalized amophous silicon films ws showon to be superior to that of the TFTs fabricated on the as-deposited polysilicon films. It was found that the performance of poly-Si TFTs depends strongly on the material characteristics of the polysilicon films used as the active layers, but only weakly on the channel dimensions.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.637-640
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• 2008

The properties of oriented poly(3-hexylthiophene-2,5-diyl) in field effect transistors (FETs) have been investigated through mechanical stretching process as the original. Silicon-based FETs shown high mobility of $0.02\;cm^2/V$ s after thermal treatment and $0.0092\;cm^2/V$ s at r.t. PET-based FETs were expected to show a similar performance in mobility to that of silicon-based FETs.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.333-336
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• 2006

High Pressure Annealing System was developed to improve the characteristics of low-temperature poly-silicon thin film transistors.. (TFTs). The high-pressure steam annealing was applied to the poly-silicon film made by rapid thermal annealing method. The carrier lifetime was investigated by Microwave detection of the Photo-Conductive Decay and the increase of carrier lifetime which indicates the reduction of the defect was observed by high-pressure steam annealing of 1MPa 600C 1hour.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 춘계학술대회 논문집
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• pp.679-680
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• 2007

• 한국태양에너지학회 논문집
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• 제33권5호
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• pp.24-33
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• 2013

Renewable energy industries, including sola cell plants, has been ever increasing ones for reducing fossil fuel consumption and strengthening national energy policy. In this paper we tried to identify occupational health hazards in solar cell-related industries operated in Korea. Poly silicon, silicon ingot and wafer, solar cell and module are major processes for producing solar cells. Poly silicon operations may cause hazards to workers from metal silicon, silanes, silicon, hydro fluoric acid and nitric acid. Solar cells could not be constructed without using metals such as aluminum and silver, acids such as hydrofluoric acid and nitric acid, bases such as sodium hydroxide and potassium hydroxide, and solvent and phosphorus chloride oxide. Workers in module assembly process may exposed to isopropanol, flux, solders that contain lead, tin and/or copper. To prevent occupational exposure to these hazards, it is essential to identify the hazards in each process and educate workers in industries with proper engineering and administrative control measures.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1442-1444
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• 1995

In this study, we confirmed that the crystallinity and the mechanical properties of polycrystalline Silicon(poly-Si) deposited on the poly-oxide are better than those of poly-Si on the conventional sacrificial layers that is CVD oxide layer or PSG. But the etch rate of poly-oxide is poor than that of the CVD oxide layer or PSG. Therefore, to make the best use of small stress and fast etch rate, we fabricated the double oxide layer; 10%-thick poly-oxide on 90%-thick CVD oxide or PSG. To estimate structure deformation by stress, we fabricated the test structures; cantilever. bridge and ring/beam structure and estimated by SEM. As the results, all structure is expressed the deformed structure by residual stress(tensile stress) and the deformation of the structure layer on the double oxide layer is small compared with that of the structure layer on the CVD oxide layer or PSG. And, the etch rate of the double oxide layer is enhanced compared with that of the poly-oxide.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.202-205
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• 2002

Polycrystalline silicon thin film transistors (poly-Si TFTs) are used in a wide variety of applications, and will figure prominently future high-resolution, high-performance flat panel display technology However, it was very difficult to fabricate high performance poly-Si TFTs at a temperature lower than 300$^{\circ}C$ for glass substrate. Conventional process on a glass substrate were limited temperature less than 600$^{\circ}C$ This paper proposes a high temperature process above 750$^{\circ}C$ using a flexible molybdenum substrate deposited hydrogenated amorphous silicon (a-Si:H) and than crystallized a rapid thermal processor (RTP) at the various temperatures from 750$^{\circ}C$ to 1050$^{\circ}C$. The high temperature annealed poly-Si film illustrated field effect mobility higher than 30 $\textrm{cm}^2$/Vs, achieved I$\sub$on//I$\sub$off/ current ratio of 10$^4$ and crystall volume fraction of 92%. In this paper, we introduce the new TFTs Process as flexible substrate very promising roll-to-roll process, and exhibit the properties of high temperature crystallized poly-Si Tn on molybdenum substrate.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.80-81
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• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• 대한전자공학회논문지SD
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• 제40권1호
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• pp.20-28
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• 2003

In this paper, we present results of the comparative analysis of the flicker phenomena in the poly-Si TFT-LCD and a-Si:H TFT-LCD arrays for the development and manufacturing of wide-area and high-quality TFT-LCD displays. We used four different types of TFTs; a-Si:H TFT, excimer laser annealed (ELA) poly-Si TFT, silicide mediated crystallization (SMC) poly-Si TFT, and counter-doped lateral body terminal (LBT), poly-Si TFT. We defined the electrical quantity of the flicker so that we could compare the flickers quantitatively for four different 40" UXGA TFT-LCDs. We identify three factors contributing to the flicker, such as charging time, kickback voltage and leakage current, and analyze how much each of three factors give rise to the flincker in the different TFT-LCD arrays. In addition, we suggest and show that, in the case of the poly-Si TFT-LCD arrays, the low-level (minimum) gate voltages should be carefully chosen to minimize the flicker because of their larger leakage currents compared with a-Si TFT-LCD arrays.