• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1123-1126
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• 2005

For creation of low temperature polycrystallinesilicon (LTPS) the line beam excimer laser annealing (ELA) is a well known and established technique in mass production. With introduction of Sequential Lateral Solidification (SLS) some aspects such as crystalline quality, throughput and flexibility regarding the substrate size could be improved, but for OLED manufacturing still further process development is necessary. This paper discusses line beam ELA and SLS techniques that might enable process engineers to make polycrystalline-silicon (poly-Si) films with a high degree of uniformity and quality as required for system on glass (SOG) and active matrix organic light emitting displays (AMOLED). Equipment requirements are discussed and compared to previous standards. SEM images of process examples are shown in order to demonstrate the viability.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.622-625
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• 2003

The dependence of stress-induced leakage current on LTPS TFTs was characterized in this study. The impacts of poly-Si crystallization, gate insulator, impurity activation, hydrogenation process and electrostatic discharge damage were investigated. It was observed more TFTs instable characteristic under those process-assisted processes. According to the LTPS roadmap, smaller geometric and low temperature process were the future trend and the stress-induced leakage current should be worthy of remark.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.343-343
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• 2010

In this paper, Schottky barrier thin-film-transistors (SB-TFTs) with platinum silicide at source/drain region based on glass substrate were fabricated. Poly-silicon on glass substrates was crystallized by excimer laser annealing (ELA) method. The formation of pt-silicide at source/drain region is the most important process for SB-TFTs fabrication. We study the optimal condition of Pt-silicidation on glass substrate. Also, we propose this device as promising structure in the future.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 춘계학술대회
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• pp.1021-1024
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• 2003

In this work, we fabricated various 2D metallic and polymeric nanopatterns with the feature resolution of sub-micrometer scale by using the method of microcontact printing ($\mu$ P) based on soft lithography. Silicon masters for the micromolding were made by e-beam lithography. Composite poly(dimethylsiloxane) (PDMS) molds were composed of a thin, hard layer supported by soft PDMS layer. Finally, monodisperse metal or polymer particles could be obtained in the prepared pattern for the application of electronic devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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• pp.69-69
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• 1999

고집적 DRAM 소자의 캐패시터 제조 공정에 있어 하부 전극을 고농도로 도핑을 하기 위한 방안의 일환으로 고체 P를 이용한 two-zone 확산법으로 다결정 실리콘에 도핑하는 방법을 채택하고 가능성을 검토하였다. 기존의 도핑방법과는 달리 불필요한 산화막을 형성하지 않고 굴곡진 표면을 따라 균일하게 고농도로 도핑할 수 있는 장점이 있다. 본 실험에서는 단결정 실리콘 및 다결정 실리콘에 대해 온도와 시간을 달리하여 P를 도핑하고, SIMS 분석으로 실험 조건에 따른 표면 농도를 분석하였다. 또한 도핑 온도를 달리하여, PH3를 이용하여 도핑한 경우와 비교 분석하였다. 표면 부근의 고농도 도핑을 위해서는 도핑온도를 저온으로 가져가고 도핑시간을 길게 가져가는 것이 유리하고, 고체 P를 사용한 경우에 있어서 PH3에 비해 표면 부근의 농도가 약 10배 정도 고농도로 도핑된 것을 알 수 있었다. 실제 소자에서의 적용 가능성을 보기 위하여, 캐패시터를 제작하여 전기적 특성을 분석하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 추계학술대회 논문집
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• pp.14-17
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• 1992

To analyze Nonvolatile SNOSFET(polySilicon-Nitride-Oxide-Semiconductor Field Effect Transistor) memory device, two dimensional numerical computer simulation program was developed. The equation discretization was performed by the Finite difference method and the solution was derived by the Iteration method. The doping profile of n-channel device which was fabricated by 1Mbit CMOS process was observed. The electrical potential and the carrier concentration distribution to applied bias condition were observed in the inner of a device. As a result of the write and the erase to memory charge quantity, the threshold voltage shift is expected. Therefore, without device fabrication, the operating characteristics of the device was observed under various the processing and the operating condition.

• Applied Science and Convergence Technology
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• 제26권5호
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• pp.129-132
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• 2017

We report a chemical vapor deposition approach and optimized growth condition to the synthesis of single layer molybdenum disulfide ($MoS_2$). Obtaining large grain size with continuous $MoS_2$ atomically thin films is highly responsible to the growth distance between molybdenum trioxide source and receiving silicon substrate. Experimental results indicate that triangular shape $MoS_2$ grain size could be enlarged up to > 80um with the precisely controlled the source-to-substrate distance under 7.5 mm. Furthermore, we demonstrate fabrication of a memory device by employing poly(methyl methacrylate) (PMMA) as insulating layer. The fabricated devices have a PMMA-$MoS_2$/metal configuration and exhibit a bistable resistance switching behavior with high/low-current ratio around $10^3$.

• 한국건축시공학회:학술대회논문집
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• 한국건축시공학회 2016년도 추계 학술논문 발표대회
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• pp.111-112
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• 2016

Lately, In case of domestic fire situation, Suffocation due to inflammables has shown higher than direct disaster of the fire among the statistics of death caused by disaster. According to study, Lightweight Hybrid Panel as using the inner or outer wall is made with Polysilicon of the inorganic material, PA and vermiculite, so we make progress to performance experiment and review the density, thermal conductivity properties.

• 한국건축시공학회:학술대회논문집
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• 한국건축시공학회 2017년도 춘계 학술논문 발표대회
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• pp.173-174
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• 2017

Recently, many experiments using industrial by-products have been going on in Korea and abroad. Most of the studies on blast furnace slag and fly ash have been conducted, and the blast furnace slag based two and three component experiments have been conducted in many places. Therefore, this study is an additional study of research using polysilicon sludge and paper ash, which is a study using existing industrial by-products based on blast furnace slag, as strength properties of alkali activator according to kind and mixing ratio and to obtain basic data do.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.295-296
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• 2005

Poly-Silicon Thin Film Transistor 응용을 위한 $SiO_2$ 박막 성장에 관한 연구로서 기존의 ICP-CVD를 이용한 실험에서 $SiH_4$ 가스대신 유기 사일렌 반응물질인 TEOS(TetraethylOrthosilicate) Source를 이용하여 APCVD 법으로 성장시켰다. $SiO_2$ 박막은 반도체 및 디스플레이 분야에서 필드산화막, 보호막, 게이트 절연막 등으로 사용되며, 이러한 산화막 증착을 TEOS를 이용하였고, 빠른 증착과 더 좋은 특성을 갖는 박막 형성을 위하여 $O_2$ 반응가스를 이용하였고, Ellipsometor, XPS 등을 이용하여 계면 특성 분석을 하였다.