• 제목/요약/키워드: poly paper

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Synthesis, Molecular and Microstructural Study of Poly-N-Vinylpyrrolidone Oximo-L-Valyl-Siliconate with IR, 1H-NMR and SEM

  • Singh, Man;Padmaja, G. Vani
    • Bulletin of the Korean Chemical Society
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    • 제31권7호
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    • pp.1869-1874
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    • 2010
  • By reducing PVP with $H_2NOH$.HCl and NaOH 2:2:1 mass ratios in aqueous ethanol, poly-N-vinyl pyrrolidone oxime [PVPO] was prepared with 92% yield. Applying the sol-gel concept, orthosilicic acid [OSA] was made by hydrolyzing TEOS with ethanol in 1:0.5 molar ratios using 1 N KOH aqueous solution as a catalyst. The OSA + PVPO + $_L$-Valine ($\alpha$-amino acid) were mixed with pure ethanolic medium in 1:2:2 mass ratios and refluxed at $78^{\circ}C$ and 6 pH for 6.5 h. A white residue of poly-N-vinyl pyrrolidone oximo-L-valyl-siliconate [POVS] appeared after 5 h. The heating of reaction mixture was stopped and the contents were brought to NTP. The residue formation of POVS was intensified with lowering a temperature and completely solidified within 5 h, was filtered using a vacuum pump with Whatmann filter paper no. 42. The residue of POVS was washed several times with 20% aqueous cold ethanolic solution and dried in vacuum chamber at $25^{\circ}C$ for 24 h. The MP was noted above $350^{\circ}C$. Structural and internal morphology were analyzed with IR and $^1H$-NMR, and SEM respectively. A drug loading and transporting ability of the POVS in water and at pH = 5 and 8 was determined chromatographically.

CVD로 성장된 다결정 3C-SiC 박막의 라만특성 (Raman Scattering Investigation of Polycrystalline 3C-SiC Thin Films Deposited on $SiO_2$ by APCVD using HMDS)

  • 윤규형;정귀상
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.197-198
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    • 2009
  • This paper describes the Raman scattering characteristics of polycrystalline (poly) 3C-SiC films, which were deposited on the thermally oxidized Si(100) substrate by the atmosphere pressure chemical vapor deposition (APCVD) method according to growth temperature. TO and LO phonon modes to 2.0m thick poly 3C-SiC deposited at $1180^{\circ}C$ were measured at 794.4 and $965.7\;cm^{-1}$ respectively. From the intensity ratio of $I_{(LO)}/I_{(TO)}$ 1.0 and the broad full width half maximum (FWHM) of TO modes, itcan be elucidated that the crystallinity of 3C-SiC forms polycrystal instead of disordered crystal and the crystal defect is small. At the interface between 3C-SiC and $SiO_2$, $1122.6\;cm^{-1}$ related to C-O bonding was measured. Here poly 3C-SiC admixes with nanoparticle graphite with the Raman shifts of D and G bands of C-C bonding 1355.8 and $1596.8\;cm^{-1}$. Using TO mode of 2.0 m thick poly 3C-SiC, the biaxial stress was calculated as 428 MPa.

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The characteristics of poly-silicon TFTs fabricated using ELA for AMOLED applications

  • Son, Hyuk-Joo;Kim, Jae-Hong;Jung, Sung-Wook;Lee, Jeoung-In;Jang, Kyung-Soo;Chung, Hok-Yoon;Choi, Byoung-Deog;Lee, Ki-Yong;Yi, Jun-Sin
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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    • pp.1281-1283
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    • 2007
  • In this paper, the properties of n-channel poly-Si TFTs with different channel widths are reported. Poly-Si fabricated using ELA on glass substrates has high quality as a material for applications such as TFT-LCDs. The fabricated n-channel TFTs have a double stack structure of oxide-nitride which acts as an insulator layer. The results show that the small channel TFTs exhibited a lower $V_{TH}$ and the wide channel TFTs had a higher $I_{DSAT}$. The nchannel poly-Si TFTs with an $I_{ON}/I_{OFF}$ value of more than $10^4$ can be reliable switching devices for AMOLED displays.

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VHF-PECVD를 이용한 다결정 실리콘 박막 증착 및 태양전지 제조 (Poly-Si Thin Film and Solar Cells by VHF-PECVD)

  • 이정철;정연식;김석기;윤경훈;송진수;박이준;권성원;임광수
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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    • pp.995-998
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    • 2003
  • This paper presents the deposition of poly-Si thin-film and fabrication of a solar cell by VHF-PECVD method. The poly-Si thin films. and pin-type solar cells are fabricated using multi-chamber cluster tool system. A 7.4% conversion efficiency was achieved from poly-Si thin film solar cells with total thickness less than $5{\mu}m$. The physical characteristic was measured by Raman spectroscopy, solar cell characteristic was measured under AM1.5 illumination.

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다결정 3C-SiC 박막 다이오드의 제작 (Fabrication of polycrystalline 3C-SiC thin film diodes)

  • 안정학;정귀상
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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    • pp.348-349
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    • 2007
  • This paper describes the electrical characteristics of polycrystalline (poly) 3C-SiC thin film diodes, in which poly 3C-SiC thin films on n-type and p-type Si wafers, respectively, were deposited by APCVD using HMDS, Hz, and Ar gas at $1180^{\circ}C$ for 3 hr. The schottky diode with Au/poly 3C-SiC/Si(n-type) structure was fabricated. Its threshold voltage ($V_d$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_D$) values were measured as 0.84 V, over 140 V, 61nm, and $2.7\;{\times}\;10^{19}\;cm^3$, respectively. The p-n junction diodes fabricated on the poly 3C-SiC/Si(p-type) were obtained like characteristics of single 3C-SiC p-n junction diodes. Therefore, poly 3C-SiC thin film diodes will be suitable microsensors in conjunction with Si fabrication technology.

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Buried Channel 4단자 Poly-Si TFTs 제작 (The Fabrication of Four-Terminal Poly-Si TFTs with Buried Channel)

  • 정상훈;박철민;유준석;최형배;한민구
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제48권12호
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    • pp.761-767
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    • 1999
  • Poly-Si TFTs(polycrystalline silicon thin film transistors) fabricated on a low cost glass substrate have attracted a considerable amount of attention for pixel elements and peripheral driving circuits in AMLCS(active matrix liquid crystal display). In order to apply poly-Si TFTs for high resolution AMLCD, a high operating frequency and reliable circuit performances are desired. A new poly-Si TFT with CLBT(counter doped lateral body terminal) is proposed and fabricated to suppress kink effects and to improve the device stability. And this proposed device with BC(buried channel) is fabricated to increase ON-current and operating frequency. Although the troublesome LDD structure is not used in the proposed device, a low OFF-current is successfully obtained by removing the minority carrier through the CLBT. We have measured the dynamic properties of the poly-Si TFT device and its circuit. The reliability of the TFTs and their circuits after AC stress are also discussed in our paper. Our experimental results show that the BC enables the device to have high mobility and switching frequency (33MHz at $V_{DD}$ = 15 V). The minority carrier elimination of the CLBT suppresses kink effects and makes for superb dynamic reliability of the CMOS circuit. We have analyzed the mechanism in order to see why the ring oscillators do not operate by analyzing AC stressed device characteristics.

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Improvement of Wet-end Performance and Paper Strength with Polyvinylamine

  • Son, Dong-Jin;Kim, Bong-Yong
    • 펄프종이기술
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    • 제37권5호통권113호
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    • pp.63-69
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    • 2005
  • This study was performed to introduce recently developed polyvinylamine as a wet-end process and paper strength improving aids. As a retention and drainage aids, high cationic charged polyvinylamine was more effective at the BCTMP and ONP stock condition than LBKP stock condition. As a dry tensile strength aid, dual system of polyvinylamine with anionic polyacrylamide was the best at the LBKP or ONP stock conditions. On the other hand, polyvinyl amine alone was better than dual system of polyvinylamine with anionic polyacrylamide at the BCTMP condition. As a wet tensile strength aid, polyvinylamine single system and dual system of polyvinylamine with anionic polyacrylamide were good at LBKP, BCTMP and ONP stock conditions. However, poly(aminoamide)-epichlorohydrin resin was good at LBKP and ONP stock conditions but efficiency of poly(aminoamide)-epichlorohydrin resin was remarkably decreased at BCTMP stock condition.

통계적 실험계획 및 분석: Gate Poly-Silicon의 Critical Dimension에 대한 계층적 분산 구성요소 및 웨이퍼 수준 균일성 (Statistical Design of Experiments and Analysis: Hierarchical Variance Components and Wafer-Level Uniformity on Gate Poly-Silicon Critical Dimension)

  • 박성민;김병윤;이정인
    • 대한산업공학회지
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    • 제29권2호
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    • pp.179-189
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    • 2003
  • Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

습도의 영향에 따른 PDMA-b-PS 친수성 블록공중합체 박막의 패턴 조절 (The Vertical and Lateral Ordering of PDMA-b-PS Block Copolymer Thin film via Control of Relative Humidity)

  • 정현중;김태준;방준하
    • Korean Chemical Engineering Research
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    • 제49권3호
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    • pp.352-356
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    • 2011
  • 리빙 프리 라디칼 중합법은 ATRP, NMP, RAFT 등의 방법이 있으며, 지난 수 십년간 매우 빠르게 발전해 왔다. 그 중에서 RAFT 중합법은 다른 방법들에 비해 최근에 학문적으로 크게 주목 받고 있다. RAFT 중합법은 다른 리빙 프리 라디칼 중합법에 합성할 수 있는 단량체의 종류나 합성의 제한이 비교적 작아서, 다양한 기능성 고분자를 쉽게 중합할 수 있으며, 합성한 고분자의 분자량 분포 또한 좁게 만들 수 있는 장점이 있다. 따라서 RAFT 중합법을 통해 다양한 형태의 블록 공중합체, 댄드리머 등을 합성하는데 이용되고 있다. 이 논문에서는 위와 같은 RAFT 중합법을 이용해, 친수성 블록을 갖는 새로운 블록 공중합체를 합성한다. Poly(ethylene-b-styrene)와 poly(ethylene-b-metharylate-bstyrene) 같은 블록 공중합체 박막을 이용해 용매 증발법에 의한 높은 수준의 정렬도를 갖는 연구가 진행, 보고되었다. 그리고 위의 2가지 연구에서 습도가 정렬도에 큰 영향을 미치는 것으로 보고되고 있다. 하지만 위의 연구에서 친수성 블록에 의한 영향을 명확하게 규명하지 못했다. 따라서 이 논문에서는 다른 친수성 블록을 갖는 poly(N,Ndimethylacrylamide-b-styrene)를 RAFT 중합법에 의해 합성하고, 이를 이용해 박막 내에서 용매 증발법 중의 습도에 의한 영향을 일반화하고자 한다.

SLS 공정을 이용한 p-type poly-Si TFT 제작에 관한 연구 (A Study on the Fabrication of p-type poly-Si Thin Film Transistor (TFT) Using Sequential Lateral Solidification(SLS))

  • 이윤재;박정호;김동환
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제51권6호
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    • pp.229-235
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    • 2002
  • This paper presents the fabrication of polycrystalline thin film transistor(TFT) using sequential lateral solidification(SLS) of amorphous silicon. The fabricated SLS TFT showed high Performance suitable for active matrix liquid crystal display(AMLCD). The SLS process involves (1) a complete melting of selected area via irradiation through a patterned mask, and (2) a precisely controlled pulse translation of the sample with respect to the mask over a distance shorter than the super lateral growth(SLG) distance so that lateral growth extended over a number of iterative steps. The SLS experiment was performed with 550$\AA$ a-Si using 308nm XeCl laser having $2\mu\textrm{m}$ width. Irradiated laser energy density is 310mJ/$\textrm{cm}^2$ and pulse duration time was 25ns. The translation distance was 0.6$\mu$m/pulse, 0.8$\mu$m/pulse respectively. As a result, a directly solidified grain was obtained. Thin film transistors (TFTs) were fabricated on the poly-Si film made by SLS process. The characteristics of fabricated SLS p -type poly-Si TFT device with 2$\mu\textrm{m}$ channel width and 2$\mu\textrm{m}$ channel length showed the mobility of 115.5$\textrm{cm}^2$/V.s, the threshold voltage of -1.78V, subthreshold slope of 0.29V/dec, $I_{off}$ current of 7$\times$10$^{-l4}$A at $V_{DS}$ =-0.1V and $I_{on}$ / $I_{off}$ ratio of 2.4$\times$10$^{7}$ at $V_{DS}$ =-0.1V. As a result, SLS TFT showed superior characteristics to conventional poly-Si TFTs with identical geometry.y.y.y.