• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.481-484
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• 2008

In order to reduce IR drop through common electrode in AMOLED, we propose a novel method to form electrical contact between highly-conductive bus lines and common electrode by using a plasma-assisted patterning of OLED layers and double deposition of the common electrode. Plasma-assisted patterning effects on OLED performance and degradation have been investigated. This patterning method caused turn-on voltage decrease, current flow increase at the same applied OLED voltages, quantum efficiency decrease, and rapid degradation at early stage during the lifetime test. However, comparable 70% luminance lifetime were obtained for both patterned and non-patterned OLEDs.

• Journal of Information Display
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• 제10권3호
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• pp.111-116
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• 2009

In this paper, a plasma-assisted patterning method for the organic layers of organic light-emitting diodes (OLEDs) and its effect on the OLED performances are reported. Oxygen plasma was used to etch the organic layers, using the top electrode consisting of lithium fluoride and aluminum as an etching mask. Although the current flow at low voltages increased for the etched OLEDs, there was no significant degradation of the OLED efficiency and lifetime in comparison with the conventional OLEDs. Therefore, this method can be used to reduce the ohmic voltage drop along the common top electrodes by connecting the top electrode with highly conductive bus lines after the common organic layers on the bus lines are etched by plasma. To further analyze the current increase at low voltages, the plasma patterning effect on the OLED performance was investigated by changing the device sizes, especially in one direction, and by changing the etching depth in the vertical direction of the device. It was found that the current flow increase at low voltages was not proportional to the device sizes, indicating that the current flow increase does not come from the leakage current along the etched sides. In the etching depth experiment, the current flow at low voltages did not increase when the etching process was stopped in the middle of the hole transport layer. This means that the current flow increase at low voltages is closely related to the modification of the hole injection layer, and thus, to the modification of the interface between the hole injection layer and the bottom electrode.

• 전자공학회논문지D
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• 제34D권3호
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• pp.87-92
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• 1997

Inductively coupled Cl$_{2}$ plasma has been studied to etch Pt thin films, which hardly form volatile compound with any reactive gas at normal process temperature. Low etch rate and residue problems are frequently observed. For higher etch rate, high density plasma and higher process temperature is adopted observed. For higher etch rate, high density plasma and higher process temperature is adopted and thus SiO$_{2}$ is used as for patterning mask instead of photoresist. The effect of O$_{2}$ or Ar addition to Cl$_{2}$ was investigated, and the chamber pressure, gas flow rate, surce RF power and bias RF power are also varied to check their effects on etch rate and selectivity. The major etching mechanism is the physical sputtering, but the ion assisted chemical raction is also found to be a big factor. The proposs can be optimized to obtain the etch rate of Pt up to 200nm/min and selectivity to SiO$_{2}$ at 2.0 or more. Patterning of submicron Pt lines are successfully demonstrated.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1273-1275
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• 2005

The influence of oxygen plasma and octadecyltrichlorosilane (OTS) treatment of $SiO_2$ on the patterning of poly(3,4-ethylenedioxythiophene)/poly(4-styrenesulfonate) (PEDOT:PSS) is presented. A significant difference in surface energies between plasma treated and OTS treated $SiO_2$ was noted. Such heterogeneous surface energy guides PEDOT:PSS to wet and spread on the wettable region and to dewet and retract from other regions.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.83-83
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• 2009

We studied about the effect of newly developed etchant for spacer etch process in gate patterning. With the 110nm CMOS technology, first, we changed the gate pattern size and investigated the variation of spacer etch profile according to the difference in gate length. Second, thickness of spacer nitride was changed and effect of etch ant on difference in nitride thickness was observed. In addition to these, spacer etch power was added as test item for variation of etch profile. We investigated the etch profiles with SEM and TEM analysis was used for plasma damage check. With these results we could check the process margins for gate patterning which could hold best performance and choose the condition for best spacer etch profile.

• 한국전기전자재료학회논문지
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• 제23권2호
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• pp.133-136
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• 2010

Laser direct patterning is one of new methods which are able to replace a conventional photolithography. In order reduce the fabrication cost and to improve the luminous efficiency of AC plasma display panels (PDPs), in this experiment, a Q-switched Nd:$YVO_4$ laser was used to fabricate T-shaped indium tin oxide (ITO) display electrodes. For the laser beam scanning speed from 100 mm/sec to 800 mm/sec, T-shaped ITO patterns were clearly obtained and investigated. The experimental results showed that the optimized T-shaped ITO electrode was obtained when the lasers scanning speed was 300 mm/s.

• 한국재료학회지
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• 제11권6호
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• pp.527-532
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• 2001

O$_2$plasma와 H(hfac)을 이용한 Cu 박막의 건식 식각을 조사하였다. 휘발성이 큰 Cu(hfac)$_2$와 $H_2O$를 탈착시키기 위하여 $O_2$ Plasma를 이용한 Cu 박막의 산화와 생성된 Cu 산화막을 H(hfac)과의 반응으로 제거하는 공정으로 식각을 수행하였다. Cu 박막의 식각율은 50-700 /min의 범위를 보였으며, 기판온도, H(hfac)/O$_2$ 유량비, plasma power에 따라 변하였다. Cu 박막의 식각율은 기판온도 215$^{\circ}C$보다 높은 온도구간에서 RF power가 증가함에 따라 증가하였고, 산화 공정과 H (hfac)과의 반응이 균형을 이루는 최적의 H (hfac)/O$_2$ 유량비는 1:1임을 확인하였다. Ti mask를 사용한 Cu Patterning은 유량비 1 : 1, 기판온도 25$0^{\circ}C$에서 실시하였고, 30$^{\circ}$외 taper slope를 갖는 등방성 etching profile을 얻을 수 있었다. Taper angle을 갖는 Cu 건식 patterning은 고해상도의 대면적 thin film transistor liquid-crystal(TFT-LCDs)를 위래 필요한 것으로써 기판온도, RF power, 유량비를 조절한 one-step 공정으로부터 성공적으로 얻을 수 있었다.

• 센서학회지
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• 제14권6호
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• pp.423-429
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• 2005

In this paper, we proposed the fabrication process of the stable e-beam evaporation and the patterning of metals layer on the polydimethylsiloxane (PDMS) substrate. The metal layer was deposited under the various deposition rate, and its effect to the electrical and mechanical properties (e.g.: adhesion-strength of metal layer) was investigated. The influence of surface roughness to the adhesion-strength was also examined via the tape test. Here, we varied the roughness by changing the reactive ion etching (RIE) duration. The electrode patterning was performed through the conventional photolithography and chemical etching process after e-beam deposition of $200{\AA}$ Ti and $1000{\AA}$ Au. As a result, the adhesion strength of metal layer on the PDMS surface was greatly improved by the oxygen plasma treatment. The e-beam evaporation on the PDMS surface is known to create the wavy topography. Here, we found that such wavy patterns do not effect to the electrical and mechanical properties. In conclusion, the metal patterns with minimum $20{\mu}m$ line width was produced well via the our fabrication process, and its electrical conductance was almost similar to the that of metal patterns on the silicon or glass substrates.

• 반도체디스플레이기술학회지
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• 제17권3호
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• pp.36-40
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• 2018

We have developed a nonlithographic patterning technique using polystyrene nanoparticles to form nanonet channel structures which is promising for high-performance TFT applications. Nanoparticles assisted patterning (NAP) is a technique to form uniform nano-patterns by applying lift-off and dry etch process. Oxygen plasma treatment was used to control the diameters of nanonet hole size to realize a branch width down to 100 nm. NAP technology can be very promising to fabricate nanonet structure with advantages of lower manufacturing cost and large-area patterning capability.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.775-777
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• 2003

Several methods are available for the fabrication of electrode pattern for the plasma display panel(PDP) including screen printing and photolithographic method. Piezo type ink-jet printing method is considered to the method of choice for electrode patterning in manufacturing of PDP. Both silver ink and absorbent layer paste formulation were developed for ink-jet printing of electrode pattern. The ink-jet printing of silver electrode with preformed absorbent layer was especially suitable for the patterning of address electrode for high resolution PDP.