• Journal of the Korean Society for Nondestructive Testing
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• v.35 no.5
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• pp.307-313
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• 2015

Leak detection in a pipeline usually involves acoustic emission sensors such as contact type sensors. These contact type sensors pose difficulties for installation and cannot operate in areas having high temperature and radiation. Therefore, recently, many researchers have studied the leak detection phenomenon by using a camera. Leak detection by using a camera has the advantages of long distance monitoring and wide area surveillance. However, the conventional leak detection method by using difference images often mistakes the vibration of a structure for a leak. In this paper, we propose a method for steam leakage detection by using the moving average of difference images and histogram analysis. The proposed method can separate the leakage and the vibration of a structure. The working performance of the proposed method is verified by comparing with experimental results.

• Geomechanics and Engineering
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• v.23 no.1
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• pp.39-50
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• 2020

In order to understand the shear mechanical properties of the interface between clay and structure and better serve the practical engineering projects, it is critical to conduct shear tests on the clay-structure interface. In this work, the direct shear test of clay-concrete slab with different joint roughness coefficient (JRC) of the interface and different normal stress is performed in the laboratory. Our experimental results show that (1) shear strength of the interface between clay and structure is greatly affected by the change of normal stress under the same condition of JRC and shear stress of the interface gradually increases with increasing normal stress; (2) there is a critical value JRC_cr in the roughness coefficient of the interface; (3) the relationship between shear strength and normal stress can be described by the Mohr Coulomb failure criterion, and the cohesion and friction angle of the interface under different roughness conditions can be calculated accordingly. We find that there also exists a critical value JRC_cr for cohesion and the cohesion of the interface increases first and then decreases as JRC increases. Moreover, the friction angle of the interface fluctuates with the change of JRC and it is always smaller than the internal friction angle of clay used in this experiment; (4) the failure type of the interface of the clay-concrete slab is type I sliding failure and does not change with varying JRC when the normal stress is small enough. When the normal stress increases to a certain extent, the failure type of the interface will gradually change from shear failure to type II sliding failure with the increment of JRC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Progress in Superconductivity and Cryogenics
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• v.8 no.2
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• pp.17-19
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• 2006

A novel clock distribution technique for pipelined-RSFQ logics using variable Bias Currents of JTLs as delay-medium is newly proposed. RSFQ logics consist of several logic gates or blocks connected in a pipeline structure. And each block has variable delay difference. In the structure, this clock distribution method generates a set of clock signals for each logic blocks with suitable corresponding delays. These delays, in the order of few to tens of pS, can be adjusted through controlling bias current of JTL of delay medium. While delays with resistor value and JJ size are fixed at fabrication stage, delay through bias current can be controlled externally, and thus, is heavily investigated for its range as well as correct operation within current margin. Possible ways of a standard delay library with modular structure are sought for further modularizing Pipelined-RSFQ applications. Simulations and verifications are done through WRSpice with Hypres 3-um process parameters.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.7
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• pp.4977-4983
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• 2015

The full depth excavation induces couple of technical and social problems like increase of construction cost and time for excavation and backfill, increase of public complains and delay of traffic, and so force. In order to overcome these problems, lots of laboratory tests were carried out for sewer pipeline of maintenance materials with trenchless methods. The testing materials are PVC strip and then the lab tests were followed by Korean Standard. We will treat the structure safety and pipe integrity of PVC profile more excellent than the profile have application to SPR. There is no side-effect to process and to satisfy the criteria of tensile strength, impact strength and softening temperature. The profile with resin adhesive showed no leakage of water at specific pressure.

• The Journal of the Convergence on Culture Technology
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• v.7 no.4
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• pp.751-757
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• 2021

In this paper, we proposed a pipeline system for holographic image production in a web server-based environment. There are time and spatial constraints for the existing holographic image production. The purpose of the proposed system is to obtain high-quality holographic images by reducing accessibility to users. It is a structure in which a video captured by a user in a web environment is transmitted to a server and converted into a frame for holographic image production through post-production. For high-quality holographic image acquisition, post-processing uses a deep learning-based algorithm. The proposed system provides various service tools in the web environment for user convenience. Through this method, the user's accessibility is improved when producing holographic images because images are taken in a web environment rather than in a limited space.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.415-418
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• 2004

This paper describes a VLSI implementation of BLAST detection for MIMO-OFDM systems. To achieve high speed requirement, we propose the fully pipeline architecture for BLAST structure. This design is implemented using $0.18{\mu}m$ CMOS technology. For a 4-transmit and 4-receive antennas system, it takes $7.5{\mu}s$ to calculate nulling vector and detection order from 48 channel matrixes.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.321-326
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• 1992

In this paper, a high performance graphics system is suggested and its hardware architecture and software structure are described. The developed graphics system is a multi-processing system that uses 6 i860 RISC CPU's and supports PHIGS language in a hardware level. The software is programmed with respect to the graphics pipeline and the software modules are distributed into each processor for the optimization of the performance. The implemented graphics system can draw about 100,000 3D polygons second.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.989-990
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• 2006

This paper presents a design of 3D Graphics Geometry processor. A geometry processor needs to cope with a large amount of computation and consists of transformation processor and lighting processor. To deal with the huge computation, a vector processing structure based on pipeline chaining is proposed. The proposed geometry processor performs 4.3M vertices/sec at 100MHz using 11 floating-point units.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.5-8
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• 2002

In this paper, we are designed and verified a FFT/IFFT processor that is possible from the wireless LAN environment which is adopted international standard of the IEEE802.11a. The proposed architecture of the FFT/IFFT has Radix-2 64point SDF(single-path delay feedback) Pipeline technique and DIF(Decimation in Frequenct) structure. The FFT/IFFT processor has each 8 bit complex input-output and 6 bit Twiddle factor. we used Max-PlusII for simulation and can see that processor is properly operated