• Journal of Applied and Pure Mathematics
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• 제4권3_4호
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• pp.151-184
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• 2022

In the article, we handle with the existence and controllability results for fractional impulsive neutral functional integro-differential equation in Banach spaces. We have used advanced phase space definition for infinite delay. State dependent infinite delay is the main motivation using advanced version of phase space. The results are acquired using Schaefer's fixed point theorem. Examples are given to illustrate the theory.

• 전자공학회논문지
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• 제51권8호
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• pp.156-164
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• 2014

Field programmable gate array 기반 시간-디지털 변환기(Time to Digital Converter)로 가장 널리 사용되는 딜레이 라인(tapped delay line) 방식은 딜레이 라인의 길이가 길어지면 정확도가 떨어지는 단점이 있다. 이에 본 논문에서는 동일한 시간 해상도를 가지면서 딜레이 라인의 길이를 줄일 수 있도록 4 위상 클럭을 사용하고 이중 상태 판별 제어부를 가지는 시간-디지털 변환기 구조를 제안한다. 4 위상 클럭 별로 딜레이 라인 구성 시 발생하는 라인 간 딜레이 오차를 줄이기 위해 입력신호와 가장 가까운 클럭과의 시간 차이만 하나의 딜레이 라인으로 측정하고 어떤 위상 클럭이 사용되었는지를 판별하는 구조를 가졌다. 또한 싱크로나이저 대신 이중 상태 측정 state machine을 이용하여 메타스태이블을 판별함으로써, 싱크로나이저로 인한 딜레이 라인의 증가를 억제하였다. 제안한 시간-디지털 변환기(TDC)의 성능 측정 결과 1 ms의 측정 시간 범위에 대해 평균 분해능 22 ps, 최대 표준편차 90 ps을 가지며 비선형성은 25 ps였다.

• 전기전자학회논문지
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• 제21권4호
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• pp.416-419
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• 2017

본 논문에서는 고속 DDR3/DDR4 SDRAM을 위한 새로운 디지털 지연고정루프 (delay-locked loop: DLL)를 제안한다. 제안하는 디지털 DLL은 디지털 지연라인의 boundary switching 문제에 의한 jitter 증가 문제를 제거하기 위하여 위상보간 (phase interpolation) 방식의 파인지연라인 (fine delay line)을 채택하였다. 또한, 제안하는 디지털 DLL은 harmonic lock 문제를 제거하기 위하여 새로운 점진직 검색 (gradual search) 알고리즘을 사용한다. 제안하는 디지털 DLL은 1.1V, 38-nm CMOS DRAM 공정으로 설계되었으며, 0.25-2.0 GHz의 주파수 동작 영역을 가진다. 2.0 GHz에서 1.1 ps의 피크-투-피크 (p-p) 지터를 가지며, 약 13 mW의 전력소모를 가진다.

• 천문학회보
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• 제41권2호
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• pp.36.2-36.2
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• 2016

In mm-VLBI, the quality of observation data is largely affected by atmospheric effect. The most challenging matter is that the phase of correlator output fluctuates rapidly resulting from a variation of atmospheric propagation delay. Consequently, it is demanding to achieve high Signal-to-Noise ratio by integrating data in time domain before calibrating atmospheric delay. However, Korean VLBI Network (KVN) has a unique system to make a 4-frequency (22/43/86/129 GHz) simultaneous observation in mm-wavelength and Frequency Phase Transfer (FPT) calibration technique has effectively removed atmospheric delay in the simultaneous multi-frequency observation of the KVN. For astrometric and astrophysical studies, we evaluated the FPT performance of KVN in various observing conditions. Using the total 38 bright AGNs, we have compared atmospheric conditions such as ground-based weather information, system temperature, atmospheric delay with the calibration results of FPT at 22/43/86/129 GHz during the five experiments in 2013, and quantified its performance in terms of coherence function and Allan variance. We present the analysis result of the relation between the FPT performance and observing conditions.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1838-1842
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• 2004

Gain and phase margins of a first order plus delayed time (FOPDT) process controlled by generalized predictive controller (GPC) are related to the control parameters ${\lambda}$ (control move suppression parameter) and ${\alpha}$ (smoothing filter coefficient) and the normalized delay of the process. Variation ranges of gain and phase margins are determined. It is shown that the margins cannot be assigned independently for a wide range of variation and the range is narrowing by increase of the normalized delay of the process. And finally curves are given to use for adjustment of the controller parameters in order to obtain a specific pair of gain and phase margins.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.415-419
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• 1996

This paper presents motor speed and phase angle detection method using a sinusoidal AC tachogenerator. The 2-phase or 3-phase output tacho-generator can be adopted, and its' output voltages must have sinusoidal waveforms. Because the detection algorithm is simple, the proposed method can be implemented with analog devices of microprocessor conveniently. And the proposed method has a very short detection delay time. Especially in the analog implementation, there is no delay time without the settling time of analog devices. With the Experimental results, it is verified that the proposed method can accurately detect the instantaneous motor speed and phase over the wide ranges.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.726-737
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• 2017

The use of energy storage systems (ESSs) has become a feasible solution to solve the wind power intermittency issue. However, the use of ESSs increases the system cost significantly. In this paper, an optimal power flow control scheme to minimize the ESS capacity is proposed by using the zero-phase delay low-pass filter which can eliminate the phase delay between the dispatch power and the wind power. In addition, the filter time constant is optimized at the beginning of each dispatching interval to ensure the fluctuation mitigation requirement imposed by the grid code with a minimal ESS capacity. And also, a short-term power dispatch control algorithm is developed suitable for the proposed power dispatch based on the zero-phase delay low-pass filter with the predetermined ESS capacity. In order to verify the effectiveness of the proposed power management approach, case studies are carried out by using a 3-MW wind turbine with real wind speed data measured on Jeju Island.

• 대한교통학회지
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• 제20권2호
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• pp.149-159
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• 2002

다이아몬드 인터체인지에서 사용되는 두 가지 유형의 3현시 신호 체계의 운영결과를 다양한 교통상황 하에서 분석하였다. 본 연구를 수행하기 위하여 Hardware-in-the-loop 장치를 CORSIM 프로그램과 연결하여 사용하였으며, 운영결과는 평균지체와 총 정지수의 두 가지 효과척도를 사용하여 평가하였다. 평가결과 두 가지 3현시 신호 체계는 평균적으로 평균지체에 관해서는 동일한 결과를 나타내었으나 총 정지수는 다른 결과를 나타내었다. 또한 평균지체는 교통패턴과 인터체인지 거리에 따라 큰 영향을 받는 것으로 파악되었다. 총 정지수는 인터체인지 거리가 증가함에 따라 감소되었고, 두 가지 3현시 신호체계의 운영효과를 비교 평가할 수 있는 척도로 평가되었다. 그리고 Hardware-in-the-loop 장치를 결합하여 현재 시뮬레이션 기술의 적용영역을 확장할 수 있음을 구현하여 예시하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.