• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.955-959
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• 2003

A technique for realizing linear phase IIR filters has been proposed by Powell-Chau which gives a real-time implementation of H(z-1).H(z), where H(z) is a causal nonlinear phase IIR filter. Powell-Chau system is linear but not timeinvariant system. Therefore, that system has group delay response that exhibits a minor sinusoidal variation superimposed on a constant value. In the signal processing, this oscillation seriously degrade the signal quality. Unfortunately, that system has a large sample delay of 4L and also more computational complexity. Proposed system is present a reduced computational complexity technique by moved the numerator polynomial of H(1/z) out to cascade with causal filter H(z) and remain only all-pole of H(1/z), then applied truncated infinite impulse response to finite with truncated IIR filtel $H_L$(z) and L sample delay to subtract the output sequence from the top and bottom filter. Proposed system is linear time invariance and group delay response and total harmonic distortion are also improved.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.241-246
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• 2016

This paper presents a method that can improve the performance of permanent magnet synchronous motor current control by minimizing the measured current phase delay caused by the Low Pass Filter(LPF) used to cut off the noises that flowed in when feedback currents are measured. Although existing methods that change the Cutoff Frequency of the LPF can minimize phase delays during high speed rotations, their noise cutoff effects are much lower and this may lead to the decline of control performance. Therefore, in this study, an algorithm that can compensate current phase delays through relatively simple calculations from the synchronous motor d-q axis coordinate transformation matrix and the inverse transformation matrix is proposed and the validity of the proposed method is verified by comparing the waveform of the calculated current with the waveform of actual currents through simulations and experiments.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.4
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• pp.88-96
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• 1997

This paper suggests a new non-linear friction compensation for digital control systems. This control adopts a hysteresis nonlinear element which can introduce the phase lead of the control system to compensate the phase delay comes from the inherent time delay of a digital control. A proper Lyapunov function is selected and the Lyapunov direct method is used to prove the asymptotic stability of the suggested control.

• Proceedings of the Acoustical Society of Korea Conference
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• 1987.11a
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• pp.79-81
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• 1987

In this paper we propose a fast adaptive least squares algorithm for linear phase FIR filters. The algorithm requires 10m multiplications per data point where m is the filter order. Both linear phase cases with constant phase delay and constant group delay are examined. Simulation results demonstrate that the proeposed algorithm is superior to the LMS gradient algorithm and the averaging scheme used for the modified fast Kalman algorithm.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.987-993
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• 1996

This report suggests a new non-linear friction compensation for digital control systems. This control adopts a hysteric nonlinear clement which can introduce the phase lead of the control system to compensate the phase delay comes from the inherent time delay of a digital control. The Lyapunov direct method is used to prove the asymtotic stability of the suggested control, and the stability and the effectiveness are verified analytically and experimentally on a single axis servo driving system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.10
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• pp.1212-1215
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• 2012

This study describes the accuracy improvement of the estimated angle using phase averaging in phase-comparison monopulse algorithm. In addition, to compensate the time-delay due to the phase averaging, we propose the time-delay compensation algorithm which uses the derivative of the estimated angle. These derivative is calculated by the curve fitting method. Using the real radar interferometer, we have verified that the phase averaging and time-delay compensation algorithms are effective in real-time signal processing application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.394-397
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• 2003

Since the speed of operation in the system has been increasing rapidly, chips should have been synchronized. Then, synchronized circuits such as PLL (Phase Locked Loop), DLL (Delay Locked Loop) are used. VCO (Voltage Controled Oscillator) generated a frequency in the PLL has disadvantage such as jitter accumulation. On the other hands, VCDL (Voltage Controled Delay Line) used at DLL has an advantage which has no jitter accumulation. In this paper, a new and improved VCDL structure is suggested.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.8-15
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• 2003

In this paper, the issue of the differential ring oscillator in designing low phase noise is linearity improvement of delay cell's load resistor. A novel differential delay cell that improves on the Maneatis load is proposed. The linearity improvement of load resistor results in lower phase noise in ring oscillator. For comparison of the phase noise characteristics, Ali Hajimiri's phase noise model is used. In order to have a low ISF(impulse sensitivity function), it is important to have a symmetry between rise time and fall time of oscillation waveform. The ISF value of ing oscillator based on the proposed delay cell is lower than that of the existing ring oscillators. Due to this result, the phase noise is improved by 2~3dBc/Hz for the same power dissipation and oscillation frequency.