• Journal of Power Electronics
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• 제19권3호
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• pp.613-624
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• 2019

Digital current control techniques are an attractive option for DC-DC converters. In this paper, a digital predictive peak current control algorithm is presented for buck converters that allows the inductor current to track the reference current in two switching cycles. This control algorithm predicts the inductor current in a future period by sampling the input voltage, output voltage and inductor current of the current period, which overcomes the problem of hardware periodic delay. Under the premise of ensuring the stability of the system, the response speed is greatly improved. A real-time parameter identification method is also proposed to obtain the precision coefficient of the control algorithm when the inductance is changed. The combination of the two algorithms achieves adaptive tracking of the peak inductor current. The performance of the proposed algorithms is verified using simulations and experimental results. In addition, its performance is compared with that of a conventional proportional-integral (PI) algorithm.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권2호
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• pp.60-64
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• 2001

The degradation process of silicone rubber was investigated by leakage current monitoring in Inclined-Plane method. DAS (Data Acquisition System) with 12-bit, 8-channel A/D converter was prepared. Average current, cumulative charge, current waveform and the number of peak pulses were measured on-line. And, FFT (Fast Fourier Transform) analysis was performed with stored current waveform. Besides, maximum erosion depth was measured in order to use as the indicator of the degradation process. So, the results of leakage current components and maximum erosion depth measurements were compared to find one or more components which have trends of changing similarly to that of erosion process. The result suggests that the ratio of peak current to r.m.s. current, harmonic contents and the number of peak pulses are well corresponding with the degradation process.

• 전자공학회논문지A
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• 제32A권7호
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• pp.51-57
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• 1995

The theoretical analysis for AlInAs/GaInAs resonant tunneling diodes (RTDs), which have shown the improved negative differential resistance (NDR) characteristics, has scarcely been made in comparison with AlGaAS/GaAs RTDs. In this paper, the static current-voltage relation of Al$_{0.48}In_{0.52}As/Ga_{0.47}In_{0.53}$As RTDs were numerically estimated by using a self-consistent method. Assuming a simplified RTD with single quantum well structure and spacer layers, the peak current density (J$_{P}$) and the peak-to-valley current ratio (PVCR) were analysed as the function of the thickness of the well, the barrier and the spacer layer, and temperature. As the results, the peak current density and the peak-to-valley current ratio indicated a reciprocal relation roughly in respect to the thicknesses of the well and the barrier, and it was theoretically predicted that it be not attainable to provide a high peak current desity (J$_{P}$) over 1${\times}10^{5}A/cm^{2}$ as well as the large peak-to-valley current ratio (PVCR) over 10 that were the the critical conditions for the practical use.

• 전자공학회논문지
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• 제53권1호
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• pp.43-50
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• 2016

낸드플래시 기반 저장장치는 성능 향상을 위해 다중 채널, 다중 웨이 구조를 통해 다수의 낸드 디바이스를 병렬 동작시키고 있다. 하지만 동시 동작하는 낸드 디바이스의 수가 늘어나면서 전력 소모 문제가 가시화되었으며, 특히 디바이스 간 복수의 피크 전류가 서로 중첩되면서 높은 전력소모로 인해 데이터 신뢰성과 시스템 안정성에 큰 영향을 미치고 있다. 본 논문에서는 낸드 디바이스에서 지우기, 쓰기, 읽기 동작에 대한 전류 파형을 측정, 이를 프로파일링하여 피크 전류에 대한 정의와 모델링을 진행하였고, 나아가 다수의 낸드에서 피크 전류 중첩 확률을 계산한다. 또한 시스템 수준의 TLM 시뮬레이터를 개발하여 다양한 시뮬레이션 시나리오를 주입하여 피크 전류 중첩 현상을 분석 한다. 본 실험 결과에서는 낸드간 피크 중첩 현상을 차단할 수 있는 간단한 전력 관리 기법을 적용하여 피크 전류 중첩과 시스템 성능 간의 관계를 살펴보고 이를 통해 성능 저하 최소화를 위한 피크 중첩 비율을 제시하였다.

• 전력전자학회논문지
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• 제3권4호
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• pp.338-345
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• 1998

The mathematical interpretation of a practical sampler which is useful to obtain the small signal models for the peak and average current mode controls is proposed. Due to the difficulties in applying the Shannons sampling theorem to the analysis of sampling effects embedded in the current mode control, several different approaches have been reported. However, these approaches require the information of the inductor current in a discrete expression, which restricts the application of the reported method only to the peak current mode control. In this paper, the mathematical expressions of sampling effects on a current loop which can directly apply the Shannons sampling theorem are newly proposed, and applied to the modeling of the peak current mode control. By the newly derived models of a practial smapler, the models in a discrete time domain and a continuous time domain are obtained. It is expected that the derived models are useful for the control loop design of power supplies. The effectiveness of the derived models are verified through the simulation and experimental results.

• Journal of Power Electronics
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• 제12권5호
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• pp.715-722
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• 2012

New discrete time domain models for the peak current controlled (PCC) power LED drivers in continuous conduction mode include for the first time the effects of the time delay in the pulse-width-modulator. Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between the two conduction modes. Especially, the time delay can provide an accurate LED current for the PCC buck converter with a wide input voltage. The models can also predict the critical inductor value at the mode boundary as functions of the input voltage and the time delay. The overshoot of the peak inductor current due to the time delay results in the increase of the average output current and the reduction of the critical inductor value at the mode boundary in all converters. Experimental results are presented for the PCC buck LED driver with constant-frequency controller.

• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.546-550
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• 2013

We propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn junction diode with depletion mode nanowire (NW) transistor, which suppress the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) Esaki diode with degenerately doped pn junction can provide multiple switching behavior having multi-peak and valley currents. These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be over $10^4$ at low operation voltage of 0.5 V in a single peak and valley current.

• 한국통신학회논문지
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• 제18권7호
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• pp.1036-1043
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• 1993

대기압 MOCVD방법으로 이중 장벽 구조의 공명 투과 소자를 제작하여 상온과 77K에서의 부저항 특성을 특정하였다. GaAs 양자 우물과 spacer, AIGaAs 장벽을 사용하여 성장온도를 변화시켜 공명 투과 소자를 제작한 결과 상온에서 2.35, 77K에서 15.3의 높은 peak-to-valley 전류비를 얻었다 컴퓨터 모의 실험에서는 coherent 투과만을 고려하여 peak 전류를 계산해서 실험치와 잘 일치하는 것을 알 수 있었다. AlGaAs 장벽에 InGaAs 양자 우물과 spacer를 사용하여 전자의 공급량을 증가시킨 구조에서는 상온에서 8.6KA/cm의 높은 peak 전류와 4.0의 큰 peak-to-valley 전류비를 얻었다.

• 한국분무공학회지
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• 제24권3호
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• pp.114-121
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• 2019

The effect of injector driving current pattern on fuel injection rate of solenoid diesel common rail injector was studied by computer simulation. The time resolved fuel injection rate and injected quantity per stroke of a common rail injector driven with the five current patterns were computer simulated. The fuel injection rate and injected quantity per stroke according to the rail pressure and fuel injection period were also computer simulated. When the common rail injector was driven with the five driving current patterns of peak & hold, there was no difference in the fuel injection rate in the peak section regardless of all the current patterns of the five cases. On the other hand, the magnitude of the hold current value influenced the injection rate and injected quantity per stroke. That is, in the current pattern of three cases where the hold current value is equal to or more than a constant value of the peak current value, the fuel injection rates for the given common rail rail pressure and injection period are same one another. On the other hand, the current pattern of the two cases, in which the hold current value is smaller than a certain value, there is a large fluctuation in the fuel injection rate.