• Proceedings of the Korean Geotechical Society Conference
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• 2000.11a
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• pp.303-310
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• 2000

A new stress path testing scheme with back pressure equalization process is proposed, to compute the settlement of clay soils based on their probable deformation mode. The proposed testing scheme minimizes the efforts for testing, otherwise numerous testing works are required to simulate the probable stress paths in the field. Furthermore, the proposed testing scheme can supply anisotropic stress paths for consolidation which cannot be possible in a conventional way. The validity and effectiveness of the proposed testing scheme was investigated and confirmed with test results on remolded kaolinite clay soils. Conclusively, it is suggested that the proposed testing scheme is a very effective tool to compute settlement of clay soils and it is also very useful to investigate the anisotropic characteristics of deformation of clay soils.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.105-112
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• 1998

In this paper, we propose a ESP(Extended Scan Path) architecture for multi-board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan path is either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using the proposed ESP architecture, we observed that the test time is short compared with the single scan path architecture. By comparing the ESP architecture with single scan path responding to independency of scan path, test time and with multi-scan path responding to signal, synchronization, we showed that the architecture has improved results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.72-84
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• 2001

The timings of all computational elements in the micropipeline circuits are important. The previous researches on path delay testing using scan methods make little account of the characteristic of the path delay tests that the second test pattern must be more controllable. In this paper, a new scan latch is proposed which is suitable to path delay testing of the micropipelines and has small area overhead. Results show that path delay faults in the micropipeline circuits using the new scan are testable robustly and the fault coverage is higher than the previous researches. In addition, the new scan latch for path delay faults testing in the micropipeline circuits can be easily expanded to the applications such as BIST for stuck-at faults.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.173-183
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• 1996

In this paper, a new structure that can do fault detection and location of digial logic circuits more efficiently using current testing techniques is proposed. In the conventional method, observation point for steady state power supply current was only one, but in the proposed method more fault classes are divided for fault detection and location through the ovservation of steady state power supply current at two points. Also, it is shown that this structure can be easily applied in detection of stuck-open fault which is not easy to do testing with conventional current testing techniques. In the presented mehtod, an extra trasnistor is used, and current path is made compulsorily in the CMOS circuits in which no current path can be established in steady state, then it can be known that stuck-open tault is in the MOS transistor on the considering current path, if this path disappears due to stuck-open fault. The validity and the effectiveness is shwon, thorugh the SPICE simulation of circuits with fault and the current path search experiment using current path search program based on transistor short model wirtten in C language on SUN sparc workstation.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.807-810
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• 1998

This paper presents BIST (Built-in self-test) techniques for detection of path delay faults in digital circuits. In the proosed BIST schemes, the shift registers make possible to concurrently generate and compact the latched test data. Therefore the test time is reduced efficiently. By reordering the elements of th shifte register based on the information of the hamming distance of each memory elements in CUt, it is possible to increase the number of path delay faults detected robustly/non-robustly. Experimental results for ISCAS'89 benchmark circuits show the efficiency of the proposed BIST techniques.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1924-1937
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• 1996

In this paper, we propose a ESP(Extended Scan Path) architecture for multi- board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan paths either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using, he proposed ESP architecture, we observed to the test time is short compared with the single scan path architecture. Because the ESP architecture uses the common bus, there are not additional signals in multi-board testing. By comparing the ESP architecture with conventional one using ISCAS '85 bench mark circuit, we showed that the architecture has improved results.

• KIPS Transactions on Software and Data Engineering
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• v.8 no.4
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• pp.137-144
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• 2019

Testing maturity is critical to the system under development with lack of experience and skills in the acquisition of the weapon systems. Defects have a huge impact on important system operations. Sharing real-time information will lead to rapid command and mission capability in submarine. DDS(Data Distribution System) is a very important information sharing system and interface between various manufacturers or data formats. In this paper, we analyze data distribution characteristics of distributed data system to group data-specific systems and proposes a test case-generation method using path search of postorder and preorder which is a tree traversal in path testing method. The proposed method reduces 73.7.% testing resource compare to existing methods.

• Journal of the Optical Society of Korea
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• v.17 no.4
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• pp.296-299
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• 2013

A low density lipoprotein (LDL) cholesterol testing device, structured with serial reflected face-to-face mirror (SRM) allowing spectrophotometry measurements, is presented. The spectrophotometry has been employed to measure the amount of light that a sample absorbs, but it generally should have had path length longer than 10 mm to secure enough sensitivity. Such requirement of path length has often been problematic in implementing a thin type of lab on a disc (LOD). We developed the SRM system which was implemented in a detection chamber with 1.4mm thickness, providing path length longer than 10mm, and thus straightforwardly being applicable to LOD as thin as a compact disc. The experimental results show that the SRM system gives not only a much thinner design compared to the conventional spectrophotometry-based LOD but also a comparable performance to already commercialized spectrometers.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• International conference on construction engineering and project management
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• 2009.05a
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• pp.250-256
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• 2009

This paper presents a robotic tower-crane system using encoder and gyroscope sensors as path tracking devices. Tower crane work is often associated with falling accidents and industrial disasters. Such problems often incur a loss of time and money for the contractor. For this reason, many studies have been done on an automatic tower crane. As a part of 5-year 23-million-dollar research project in Korea, we are developing a robotic tower crane which aims to improve the safety level and productivity. We selected a luffing tower crane, which is commonly used in urban construction projects today, as a platform for the robotic tower crane system. This system comprises two modules: the automated path planning module and the path tracking module. The automated path planning system uses the 3D Cartesian coordinates. When the robotic tower crane lifts construction material, the algorithm creates a line, which represents a lifting path, in virtual space. This algorithm seeks and generates the best route to lift construction material while avoiding known obstacles from real construction site. The path tracking system detects the location of a lifted material in terms of the 3D coordinate values using various types of sensors including adopts encoder and gyroscope sensors. We are testing various sensors as a candidate for the path tracking device. This specific study focuses on how to employ encoder and gyroscope sensors in the robotic crane These sensors measure a movement and rotary motion of the robotic tower crane. Finally, the movement of the robotic tower crane is displayed in a virtual space that synthesizes the data from two modules: the automatically planned path and the tracked paths. We are currently field-testing the feasibility of the proposed system using an actual tower crane. In the next step, the robotic tower crane will be applied to actual construction sites with a following analysis of the crane's productivity in order to ascertain its economic efficiency.