• 전자공학회논문지B
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• 제31B권10호
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• pp.67-72
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• 1994

In this paper we suggest a 32 bit high speed parallel multiplier which plays an important role in digital signal processing. We employ a bit-pair recoding Booth algoritham that gurantees n/2 partial product terms, which uniformly handles the signed-operand case. While partial product terms are generated, a special method is suggested to reduce time delay by employing 1's complement instead of 2's complement. Later when partial products are added, the additional 1 bit's are packed in a single partial product term and added to in the parallel counter. Then 16 partial product terms are reduced to two summands by using successive parallel counters. Final multiplication value is obtained by a BLC adder. When this multiplier is simulated under 0.8$\mu$CMOS standard cell we obtain 30ns multiplier speed.

• 대한수학회보
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• 제53권2호
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• pp.495-506
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• 2016

In this note we consider the monoid $\mathcal{PODI}_n$ of all monotone partial permutations on $\{1,{\ldots},n\}$ and its submonoids $\mathcal{DP}_n$, $\mathcal{POI}_n$ and $\mathcal{ODP}_n$ of all partial isometries, of all order-preserving partial permutations and of all order-preserving partial isometries, respectively. We prove that both the monoids $\mathcal{POI}_n$ and $\mathcal{ODP}_n$ are quotients of bilateral semidirect products of two of their remarkable submonoids, namely of extensive and of co-extensive transformations. Moreover, we show that $\mathcal{PODI}_n$ is a quotient of a semidirect product of $\mathcal{POI}_n$ and the group $\mathcal{C}_2$ of order two and, analogously, $\mathcal{DP}_n$ is a quotient of a semidirect product of $\mathcal{ODP}_n$ and $\mathcal{C}_2$.

• 대한수학회지
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• 제52권4호
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• pp.869-889
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• 2015

Let ${\Gamma}^+$ be the positive cone in a totally ordered abelian group ${\Gamma}$, and ${\alpha}$ an action of ${\Gamma}^+$ by extendible endomorphisms of a $C^*$-algebra A. Suppose I is an extendible ${\alpha}$-invariant ideal of A. We prove that the partial-isometric crossed product $\mathcal{I}:=I{\times}^{piso}_{\alpha}{\Gamma}^+$ embeds naturally as an ideal of $A{\times}^{piso}_{\alpha}{\Gamma}^+$, such that the quotient is the partial-isometric crossed product of the quotient algebra. We claim that this ideal $\mathcal{I}$ together with the kernel of a natural homomorphism $\phi:A{\times}^{piso}_{\alpha}{\Gamma}^+{\rightarrow}A{\times}^{iso}_{\alpha}{\Gamma}^+$ gives a composition series of ideals of $A{\times}^{piso}_{\alpha}{\Gamma}^+$ studied by Lindiarni and Raeburn.

• 충청수학회지
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• 제35권3호
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• pp.235-242
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• 2022

In this paper, we consider the existence of nonconstant warping functions on a warped product manifold M = B × _f² F, where B is a q(> 2)-dimensional base manifold with a nonconstant scalar curvature S_B(x) and F is a 3- dimensional fiber Einstein manifold and discuss that the resulting warped product manifold is an Einstein manifold, using the existence of the solution of some partial differential equation.

• 정보처리학회논문지A
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• 제10A권6호
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• pp.671-676
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• 2003

본 논문에서는 고속 병렬 곱셈기에서 속도향상을 위해 부분 곱을 가산하는 과정에 구성되는 CSA(Carry Select Adder) 트리에 새로운 압축기를 적용한 새로운 첫 번째 부분 곱가산(First Partial Product Addition : FPA)를 제안하여 기존의 전가산기를 이용한 병렬가산기보다 부분곱을 계산하는 속도를 약 20% 개선할 수 있게 했다. 새로운 회로는 새로운 FPA 구조를 사용하여 최종 합 CLA 비트를 N/2로 줄인다. 2.5v 0.25um CMOS 기술을 이용하여 제작된 16${\times}$16 곱셈기는 5.14nS의 곱셈 고속을 얻었다. 이 곱셈기의 구조는 파이프라인 설계에 용이하며 고성능을 낸다.

• Korean Journal of Mathematics
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• 제27권3호
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• pp.819-830
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• 2019

This paper is mainly concerned with the existence and uniqueness of fixed points of $f:X^k{\rightarrow}X$, $k{\in}{\mathbb{N}}$, where X is a quasi-partial metric space and mapping f satisfies appropriate conditions. Results are also supported with relevant examples.

• Korean Journal of Mathematics
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• 제17권4호
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• pp.361-374
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• 2009

We characterize a fuzzy partial order relation using its level set, find sufficient conditions for the image of a fuzzy partial order relation to be a fuzzy partial order relation, and find sufficient conditions for the inverse image of a fuzzy partial order relation to be a fuzzy partial order relation. Also we define a fuzzy lattice as fuzzy relations, characterize a fuzzy lattice using its level set, show that a fuzzy totally ordered set is a distributive fuzzy lattice, and show that the direct product of two fuzzy lattices is a fuzzy lattice.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.377-380
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• 2001

In this paper, we propose new partial product compressor and ENMODL (Enhanced-NORA-MODL) CLA(Carry Look-ahead Adder) for high speed and low power multiplier. To reduce transistor count, area, power we developed two new-approaches. One is small size partial product compressor, the other is dynamic CMOS logic ENMODL CLA. The transistor count of new compressor is reduced by 11% as compared with that of conventional one. The speed of ENMODL CLA is increased by 6.27% as compared with NMODL CLA.

• 지식경영연구
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• 제15권4호
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• pp.207-221
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• 2014

Due to the awareness for the importance of social capital, many researches have investigated that social capital contributes to the successful implementation of product innovation. Although most researchers tried to model the effect of social capital on product innovation as a linear relation, we consider it too simplistic and fuzzy because knowledge utilization which ultimately leads to product innovation should exist in the relationship between social capital and product innovation. Using 107 survey data, this study found there is a partial mediating effect of knowledge utilization on the link between structure aspect of social capital and product innovation (i.e., new product development and improvement in existing products). Next, this study reported knowledge utilization does act as a perfect mediating variable on the link between awareness aspect of social capital and improvement of existing products, but act as a partial mediating variable on the link between awareness aspect of social capital and new product development. Finally, this study found that knowledge utilization does not act as a mediating variable on the link between relation aspect of social capita and product innovation.

• 스마트미디어저널
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• 제3권1호
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• pp.39-45
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• 2014

제곱연산은 승수와 피승수가 동일한 곱셈의 특수한 경우로 병렬 제곱기의 부분곱 행렬에서 부분곱 비트들은 대칭을 이룬다. 이런 특성을 이용하여 부분곱을 폴딩(folding), 쉬프트, 재배열하여 부분곱 비트의 수와 부분곱 행렬의 최대높이들 감소시킨다. 본 논문에서는 제어신호에 따라 unsigned와 signed 제곱기로 동작하는 겸용 제곱기의 효율적인 설계 방법을 제안한다. 기존 겸용 제곱기와 달리 자리수(weight)가 다른 특정 부분곱 비트들의 덧셈에 대해 덧셈기를 사용하지 않고 계산하는 방법을 제안한다. 시뮬레이션을 통해 제안한 겸용 제곱기는 기존 겸용 제곱기와 비교하여 면적은 약 18%, 지연시간(propagated delay time)은 약 11%, 전력소모는 약 9% 감소시킬 수 있음을 보인다.