• Journal of Communications and Networks
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• v.15 no.1
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• pp.71-76
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• 2013

A new class of quantum low-density parity-check (LDPC) codes whose parity-check matrices are dual-containing matrices constructed based on lines of Euclidean geometries (EGs) is presented. The parity-check matrices of our quantum codes contain one and only one 4-cycle in every two rows and have better distance properties. However, the classical parity-check matrix constructed from EGs does not satisfy the condition of dual-containing. In some parameter conditions, parts of the rows in the matrix maybe have not any nonzero element in common. Notably, we propose four families of fascinating structure according to changes in all the parameters, and the parity-check matrices are adopted to satisfy the requirement of dual-containing. Series of matrix properties are proved. Construction methods of the parity-check matrices with dual-containing property are given. The simulation results show that the quantum LDPC codes constructed by this method perform very well over the depolarizing channel when decoded with iterative decoding based on the sum-product algorithm. Also, the quantum codes constructed in this paper outperform other quantum codes based on EGs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.50-57
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and compared with the previous results.

• ETRI Journal
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• v.27 no.5
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• ETRI Journal
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• v.29 no.3
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• pp.381-389
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• 2007

In this paper we propose a graph-theoretic method based on linear congruence for constructing low-density parity check (LDPC) codes. In this method, we design a connection graph with three kinds of special paths to ensure that the Tanner graph of the parity check matrix mapped from the connection graph is without short cycles. The new construction method results in a class of (3, ${\rho}$)-regular quasi-cyclic LDPC codes with a girth of 12. Based on the structure of the parity check matrix, the lower bound on the minimum distance of the codes is found. The simulation studies of several proposed LDPC codes demonstrate powerful bit-error-rate performance with iterative decoding in additive white Gaussian noise channels.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.473-476
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• 2004

Low-Density Parity-Check (LDPC) codes are recently emerged due to its excellent performance to use. However, the parity check matrices (H) of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix for partially parallel decoder structures, which is efficient in hardware implementation of both decoders and encoders. Using proposed methods, the encoding design can become practical while keeping the hardware complexity of partially parallel decoder structures.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.1-8
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• 2008

Low Density Parity Check codes(LDPC) are recently focused on communication systems due to its good performance. The standard of WiBro has also included LDPC codes as a channel coding. The weak point of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which limit throughput. In this paper, we propose semi-parallel architecture by using cyclic shift registers and exclusive-OR without conventional Matrix Vector Multipliers over the standard parity check matrices with Circulant Permutation Matrices(CPM). Furthermore, multi-rate encoder is designed by using proposed architecture. Our encoder with multi-rate for IEEE 802.16e LDPC has lower clock cycles and higher throughput.

• Transactions of the Society of Information Storage Systems
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• v.3 no.3
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• pp.126-128
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• 2007

일반적으로 주어진 하나의 H matrix 로 다수의 코드율을 가지는 코드화가 가능하다. 하지만 Low Density Parity Check(LDPC) 코드의 H matrix는 H matrix 내의 1의 개수와 위치에 따라 그 성능이 달라짐으로 해서 하나의 H matrix로 다수의 코드율을 대응하기 위한 설계 방법이 요구된다. H matrix 의 성능은 일반적으로 girth나 minimum distance에 의해 좌우되고 H matrix의 1의 위치에 따라 달라진다. 본 논문에서는 H matrix의 girth 와 minimum distance에 입각한 다수 개의 코드율이 대응 가능한 LDPC code의 H matrix 설계 방법을 제시하고자 한다. 이렇게 함으로써 하나의 H matrix로 다수의 코드율에 따른 각각의 성능을 일정 수준 이상 유지하는 multi-rate LDPC code가 가능하다.

• Smart Media Journal
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• v.2 no.2
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• pp.39-43
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• 2013

In this paper, we suggest a new technique for WPC parity-check matrix (H-matrix) generation and a corresponding decoding process. The key idea is to construct WPC H-matrix by using a convolutional encoder. It is easy to have many different coderates from a mother code with convolutional codes. However, it is difficult to have many different coderates with LDPC codes. Constructing LDPC Hmatrix based on a convolutional code can easily bring the advantage of convolutional codes to have different coderates. Moreover, both LDPC and convolutional decoding algorithms can be applied altogether in the decoding part. This process prevents the performance degradation of short-length WPC code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.14-19
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• 2006

The high encoding complexity of LDPC codes can be solved by designing structured parity-check matrix. If the parity-check matrix of LDPC codes is composed of same type of blocks, decoder implementation can be simple, this structure allow structured decoding and required memory for storing the parity-check matrix can be reduced largely. In this parer, we propose a construction algorithm for short block length structured LDPC codes based on girth condition, PEG algorithm and variable node connectivity. The code designed by this algorithm shows similar performance to other codes without structured constraint in low SNR and better performance in high SNR than those by simulation

• Journal of Communications and Networks
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• v.13 no.3
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• pp.205-210
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• 2011

This paper presents an approach to the construction of multiple-rate quasi-cyclic low-density parity-check (LDPC) codes. Parity-check matrices of the proposed codes consist of $q{\times}q$ square submatrices. The block rows and block columns of the parity-check matrix correspond to the hyperplanes (${\mu}$-fiats) and points in Euclidean geometries, respectively. By decomposing the ${\mu}$-fiats, we obtain LDPC codes of different code rates and a constant code length. The code performance is investigated in term of the bit error rate and compared with those of LDPC codes given in IEEE standards. Simulation results show that our codes perform very well and have low error floors over the additive white Gaussian noise channel.