Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Efficient LDPC coding using a hybrid H-matrix

  • Kim Tae Jin (Department of Electronic Engineering, Soongsil University) ;
  • Lee Chan Ho (Department of Electronic Engineering, Soongsil University) ;
  • Yeo Soon Il (Basic Research Laboratory, Electronics and Telecommunications Research Institute) ;
  • Roh Tae Moon (Basic Research Laboratory, Electronics and Telecommunications Research Institute)
  • Published : 2004.08.01
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Abstract

Low-Density Parity-Check (LDPC) codes are recently emerged due to its excellent performance to use. However, the parity check matrices (H) of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix for partially parallel decoder structures, which is efficient in hardware implementation of both decoders and encoders. Using proposed methods, the encoding design can become practical while keeping the hardware complexity of partially parallel decoder structures.

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