• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.89-96
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• 2013

The graphic processor unit (GPU) has been developed to process not only graphic data but also general system data. It shows a better performance than CPU in algorithm for 3D graphics and parallel program. In order to execute algorithm for CPU on GPU, we should understand about GPU architectures and rewrite program considering parallel processing capability and new memory model of GPU. For this reasons, a performance prediction model for the algorithm and its predicted performance through GPU system are required. These can predict problems in GPU application development or construct a performance evaluation standard for GPU. In this paper, we applied the AES encryption algorithms on our performance model and accomplished performance prediction with high accuracy under a heavy workload.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.141-149
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• 2013

This paper presents a high-speed intrusion detection process for multi-core video surveillance systems. The high-speed intrusion detection was designed to a parallel process. Based on the analysis of the conventional process, a parallel intrusion detection process was proposed so as to be accelerated by utilizing multiple processing cores in contemporary computing systems. The proposed process performs the intrusion detection in a per-frame parallel manner, considering the data dependency between frames. The proposed process was validated by implementing a multi-threaded intrusion detection program. For the system having eight processing cores, the detection speed of the proposed program is higher than that of the conventional one by up to 353.76% in terms of the frame rate.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.2
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• pp.109-120
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• 2001

In this paper, we propose the design and implementation of a portable, extensible, and efficient performance visualization framework for high performance parallel program development. The framework adopts a layered architecture:consists of three independent layers instrumentation layer, trace interface layer and visualization layer. The instrumentation layer was constructed as an ECL which captures generated events, and the EDL/JPAL constitutes the trace interface layer to provide problem-oriented interfaces between visualization layer and instrumentation layer. Finally, the visualization layer was designed as plug-and-play style for easy elimination, addition and composition of various filters, views and view groups, The proposed performance visualization framework is expected to be used as an independent performance debugging and analysis tool and as a core component in an integrated parallel programming environment.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.549-560
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• 2001

Cluster system provides attractive scalability in terms of compution power and memory size. With the advances in high speed computer network technology, cluster systems are becoming increasingly competitive compared to expensive MPPs (massively parallel processors). Load balancing is very important issue since an inappropriate scheduling of tasks cannot exploit the true potential of the system and can offset the gain from parallelization. In parallel processing program, it is difficult to predict the load of each task before running the program. Furthermore, tasks are interdependent each other in many ways. The dynamic load balancing algorithm, which evaluates each processor's load in runtime, partitions each task into the appropriate granularity and assigns them to processors in proportion to their performance in cluster systems. However, if the communication cost between processing nodes is expensive, it is not efficient for all nodes to attend load balancing process. In this paper, we restrict a processor that attend load balancing by the communication cost and the deviation of its load from the average. We simulate various models of the cluster system with parameters such as communication cost, node number, and range of workload value to compare existing load balancing methods with the proposed dynamic algorithms.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.47 no.2
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• pp.107-115
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• 2024

With the advent of the 4th Industrial Revolution, changes in the market environment and employment environment are accelerating due to smart technological innovation, and securing professional manpower and developing human resources for domestic small and medium-sized enterprises is becoming very important. Recently, most of the domestic small and medium-sized enterprises are experiencing hiring difficulties, and the development and training of human resources to overcome this is still lacking in systemization, despite much support from the government. This reflects the reality that it is not easy to invest training costs and time to adapt new employees to small and medium-sized businesses. Based on these problems, the work-study parallel project was introduced to cultivate practical talent in small and medium-sized businesses. Work-study parallel training is carried out in the form of mentoring between corporate field teachers and learning workers in actual workplaces, and even if the training is the same, there are differences depending on the learner's attitude, learning motivation, and training achievement. Ego state is a theory that can identify personality types and has the advantage of being able to understand and acknowledge oneself and others and intentionally improve positive factors to induce optimized interpersonal relationships. Accordingly, the purpose of this study is to analyze the attitudes of learning workers, who are the actual subjects for improving the performance of work-study parallel projects and establishing a stable settlement within the company, based on their ego status. Through this study, we aim to understand the impact of the personality type of learning workers on training performance and to suggest ways to improve training performance through work-study parallelism.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1902-1918
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• 1993

Parallel architecture based on the von Neumann computation model has a limitation as a massively parallel architecture due to its inherent drawback of architectural features. The data-flow model of computation has a high programmability in software perspective and high scalability in hardware perspective. However, the practical programming and experimentaion of date-flow architectures are hardly available due to the absence of practical data-flow, we present a programming environment for performing the data-flow computation on conventional parallel machines in general, loosely compled multiprocessor system in particular. We build an emulator for tagged token data-flow architecture on the iPSC/2 hypercube, a loosely coupled multiprocessor system. The emulator is a shallow layer of software executing on an iPSC/2 system, and thus makes the iPSC/2 system work as a data-flow architecture from the programmer`s viewpoint. We implement various numerical and non-numerical algorithm in a data-flow assembler language, and then compare the performance of the program with those of the versions of conventional C language, Consequently, We verify the effectiveness of this programming environment based on the emulator in experimenting the data-flow computation on a conventional parallel machine.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.8
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• pp.34-41
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• 2005

A parallel computing technique was applied to large scale structure analysis or aerodynamic design and it is a essential element in reducing the huge computation time for large scale design problem. We can use a many computers for reducing the analysis time of multidisciplinary design optimization. But previous MDO frameworks can not support a parallel design process technique so still existing which calls an analysis program continuously. In this paper, We developed a MDO framework(MLR) which supports a parallel design process to solve sequential analysis call. Finally, three sample cases are presented to show the efficiency of design time using the suggested MDO framework.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.289-293
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• 2000

We propose two new algorithms for parallelism-independent scheduling. The machine code generated from the compiler using these algorithms in its scheduling phase is parallelism-independent code, executable in minimum time regardless of the number of the processors in the parallel computer. Our new algorithms have the following phases: finding the minimum number of processors on which the program can be executed in minimal time, scheduling by an heuristic algorithm for this predefined number of processors, and serialization of the parallel schedule according to the earliest start time of the tasks. At run time tasks are taken from the serialized schedule and assigned to the processor which allows the earliest start time of the task. The order of the tasks decided at compile time is not changed at run time regardless of the number of the available processors which means there is no out-of-order issue and execution. The scheduling is done predominantly at compile time and dynamic scheduling is minimized and diminished to allocation of the tasks to the processors. We evaluate the proposed algorithms by comparing them in terms of schedule length to the CP/MISF algorithm. For performance evaluation we use both randomly generated DAGs (directed acyclic graphs) and DACs representing real applications. From practical point of view, the algorithms we propose can be successfully used for scheduling programs for in-order superscalar processors and shared memory multiprocessor systems. Superscalar processors with any number of functional units can execute the parallelism-independent code in minimum time without necessity for dynamic scheduling and out-of-order issue hardware. This means that the use of our algorithms will lead to reducing the complexity of the hardware of the processors and the run-time overhead related to the dynamic scheduling.

• Journal of the Korea Society of Computer and Information
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• v.11 no.4 s.42
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• pp.35-45
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• 2006

RIn this paper. we describe real-time parallel processing simulator developed for the use of performance analysis of rolling missiles. The real-time parallel processing simulator developed here consists of seeker emulator generating infrared image signal on aircraft, real-time computer, host computer, system unit, and actual equipments such as auto-pilot processor and seeker processor. Software is developed according to the design requirements of mathematic model, 6 degree-of-freedom module, aerodynamic module which are resided in real-time computer. and graphic user interface program resided in host computer. The real-time computer consists of six TI C-40 processors connected in parallel. The seeker emulator is designed by using analog circuits coupled with mechanical equipments. The system unit provides interface function to match impedance between the components and processes very small electrical signals. Also real launch unit of missiles is interfaced to simulator through system unit. In order to use the real-time parallel processing simulator developed here as a performance analysis equipment for rolling missiles, we perform verification test through experimental results in the field.

• Journal of Practical Engineering Education
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• v.10 no.2
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• pp.139-148
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• 2018

This study suggests the direction of management theory education in business administration under the university-linked program of Korean work and study in parallel policy. As a social science, business education is essentially to cultivate people of talent capable of making the right decisions in the social phenomenon (business practices) rather than educate skills for solving a specific issue. At the same time, the parallel system is aimed at cultivating talented people who can work practically in the real field. Therefore, practical education and theoretical education should be linked organically, and the theoretical education should be layered. Also, management education should be guaranteed to be timely and cultivate fusion thinking. Based on this background, this study is expected to contribute to the upgrading of the parallel system and education level in the future by reviewing the curriculum of the business administration department of domestic universities.