• Journal of the Korean Wood Science and Technology
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• v.23 no.3
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• pp.23-27
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• 1995

Several characteristic results of physical and optical properties of paper treated by UV light were obtained in the previous papers(Kim et al. 1988). In this paper, folding endurance and brightness of paper prepared by spraying photostabilizer were examined in order to elucidate photodegradation phenomena, UV light absorber and radical scavenger were most effective in preventing of folding endurance decrease. These results may be indicated that depolymerization of cellulose and hemicellulose chains leading to degradation of paper mechanical properties mainly caused by radical reaction. Ineffective hydroperoxide decomposer may be explained because of auto-oxidation reactions before forming stable compound from hydroperoxide.

• Communications of Mathematical Education
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• v.20 no.3 s.27
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• pp.469-482
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• 2006

It ill give much interest both to the teacher and student that paper crane makes interesting mathematical investment possible. It is really possible for the middle school students to invest mathematical activity such as the things about triangle and square, resemblance, Pythagorean theorem. I reserched how this mathematical investment possible through folding and unfolding paper crane and analyzed the mathematical meaning.

• Journal of Korea Technical Association of The Pulp and Paper Industry
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• v.45 no.1
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• pp.1-5
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• 2013

Printing papers published in between 1950's and 1990's were treated with three methods such as distilled water washing, $CaCO_3$ solution washing and methyl cellulose solution coating for improving their conservational properties. Accelerated aging with $80^{\circ}C$ and 80% RH for 14 days was applied to the testing papers. Results showed that distilled water and $CaCO_3$ washing kept increased pH even after accelerated aging, but did not improve folding endurances for 1950's-60's papers. Methyl cellulose treatment did not increased pH of the old papers, but increased folding endurances remarkably for 1950's-60's papers even after accelerated aging. It suggests that methyl cellulose treatment after $CaCO_3$ washing should give improvements both in pH and folding endurance.

• Communications of Mathematical Education
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• v.22 no.1
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• pp.65-77
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• 2008

In this paper we study new proofs and generalization of Haga theorem in paper folding. We analyze developed new proofs of Haga theorem, compare new proofs with existing proof, and describe some difference of these proofs. We generalize Haga second theorem, and suggest simple proof of generalized Haga second theorem.

• Journal for History of Mathematics
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• v.36 no.1
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• pp.1-17
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• 2023

Paper folding is a versatile tool that can be used not only as a mathematical model for analyzing the geometric properties of plane and spatial figures but also as a visual method for finding the real roots of polynomial equations. The historical evolution of origami's geometric and algebraic techniques has led to the discovery of definitions and properties that can enhance one's cognitive understanding of mathematical concepts and generate mathematical interest and motivation on an emotional level. This paper aims to examine the history of origami geometry, the utilization of origami for solving polynomial equations, and the process of determining the real roots of quadratic, cubic, and quartic equations through origami techniques.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.657-660
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• 2000

This paper proposes a Data-Flow-Graph (DFG) restructuring to reduce calculating errors in loop folding scheduling. The prime cause of calculating error is rounding errors due to the restriction of the operation digit of functional units. This rounding error is increased more by using multipliers than adders, so reducing the number of multiplications and putting off them as much as possible reduce rounding errors. The proposed approach reduces the number of multiplications by restructuring DFG in loop folding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.198-204
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• 2001

In this paper, a 3V 8-bit 200MSPS CMOS folding / interpolation A/D Converter is proposed. It employs an efficient architecture whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improved SNDR by to be low input frequency, distributed track and hold circuits are included. In order to obtain a high speed and low power operation, further, a novel dynamic latch and digital encoder based on a novel delay error correction are proposed. The chip has been fabricated with a 0.35${\mu}{\textrm}{m}$ 2-poly 3-metal n-well CMOS technology. The effective chip area is 1070${\mu}{\textrm}{m}$$\times$650${\mu}{\textrm}{m}$ and it dissipates about 230mW at 3.3V power supply. The INL is within $\pm$1LSB and DNL is within $\pm$1LSB, respectively. The SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• Proceedings of the Korea Technical Association of the Pulp and Paper Industry Conference
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• 2008.04a
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• pp.282-289
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• 2008

• Structural Engineering and Mechanics
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• v.11 no.2
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• pp.211-219
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• 2001

This paper presents the tangent stiffness method for 3-D geometrically nonlinear folding analysis of a reversal arch. Experimental tests are conducted to verify the numerical analysis. The tangent stiffness method can accurately evaluate the geometrical nonlinearity due to the element translating as a rigid body, and the method can exactly handle the large rotation of the element in space. The arch in the experiment is made from a thin flat bar, and it is found that the folding process of the arch may be captured exactly by the numerical analysis with a model consisting of only 18 elements with the same properties.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.