• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.1
• /
• pp.21-26
• /
• 2013

This study presents new analysis method to predict bending behavior of packaging substrate structure by comparing finite element method simulation and measured curvature using 3D scanner. Packaging substrate is easily bent and deflected while undergoing various processes such as curing of prepreg and copper pattern plating. We prepare specimens with various conditions and measure contours of each specimen and compute the residual stresses on deposited films using analytical solution to find the principle of bending. Core and prepreg in packaging substrate are made up of resin and bundles of fiber which exist orthogonally each other. Anisotropic material properties cause peculiar bending behavior of packaging substrate. We simulate the bending deflection with finite element method and verify the simulated deflection with measured data. The plating stress of electrodeposited copper is about 58 MPa. The curing stresses of solder resist and prepreg are about 13 MPa and 6.4 MPa respectively in room temperature.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.09a
• /
• pp.53-68
• /
• 2002

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2001.09a
• /
• pp.147-164
• /
• 2001

1. "MLS", state of the art MCM-D wiring substrate. 2. High pin-count LSl assembly. 3. Higher speed needs higher packaging density. 4. Wiring substrate, the key of LSl packaging device. 5. "Inter-Layer Transferability", a new index for the performance of wiring substrates. 6. "MLTF package", a core-less flexible package for high pin-count LSl.

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.1
• /
• pp.39-44
• /
• 2008

In this paper, fully embedded 2.4GHz WLAN band pass filter (BPF) was investigated into a multi-layered organic packaging substrate using high Q spiral stacked inductors and high Dk MIM capacitors for low cost RF System on Package (SOP) applications. The proposed 2.4GHz WLAN BPF was designed by modifying chebyshev second order filter circuit topology. It was comprised of two parallel LC resonators for obtaining two transmission zeros. It was designed by using 2D circuit and 3D EM simulators for finding out optimal geometries and verifying their applicability. It exhibited an insertion loss of max -1.7dB and return loss of min -l7dB. The two transmission zeros were observed at 1.85 and 6.7GHz, respectively. In the low frequency band of $1.8GHz{\sim}1.9GHz$, the stop band suppression of min -23dB was achieved. In the high frequency band of $4.1GHz{\sim}5.4GHz$, the stop band suppression of min -l8dB was obtained. It was the first embedded and the smallest one of the filters formed into the organic packaging substrate. It has a size of $2.2{\times}1.8{\times}0.77mm^3$.

• Journal of the Microelectronics and Packaging Society
• /
• v.31 no.2
• /
• pp.16-22
• /
• 2024

With advances of artificial intelligence (AI) technology, the demand is increasing for high-end semiconductors in various places such as data centers. In order to improve the performance of semiconductors, reducing the pitch of patterns and increasing density of I/Os are required. For this issue, 2.5dimension(D) packaging is gaining attention as a promising solution. The core technologies used in 2.5D packaging include microbump, interposer, and bridge die. These technologies enable the implementation of a larger number of I/Os than conventional methods, enabling a large amount of information to be transmitted and received simultaneously. This paper proposes the Molded Bridge die on Substrate (MBoS) process technology, which combines molding and Redistribution Layer (RDL) processes. The proposed MBoS technology is expected to contribute to the popularization of next-generation packaging technology due to its easy adaption and wide application areas.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.557-558
• /
• 2008

This paper presents the effects of via losses to be connected with an embedded DPDT(Double Pole Double Thru) in a substrate. The substrate consists of two ABF(Ajinomoto Bonding Film) and a Epoxy core. In order to verify and test effects of via, via chains in a substrate using SoP-L process are proposed and measured. Via loss can be calculated as averaging the total via holes. The exact loss of a DPDT switch embedded in substrate are extracted by using the results of via chain and measured data from embedded DPDT. The calculated one via insertion loss is about 0.0005 dB on basis of measured via chains. This result confirms very low loss in via. So the inserti on loss of the embedded switch is confirmed only switch loss as loss is 0.4 dB.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.10
• /
• pp.826-831
• /
• 2009

In this paper, a high power RF amplifier module using AlN substrate of high thermal conductivity has been proposed. This RF amplifier module has the advantage of compact size and effective heat dissipation for the packaging of high power chip. To fabricate the thru-hole and scribing line on AlN substrate, the key parameters of $CO_2$ laser were experimented. And then, microstrip lines and spiral planar inductors were fabricated on an AlN substrate using the thin-film process. The fabricated microstrip lines on the AlN substrate has an attenuation value of 0.1 dB/mm up to 10 GHz. The fabricated spiral planar inductor has a high quality factor, a maximum of about 62 at 1 GHz for a 5.65 nH inductor. Packaging of a RF power amplifier was implemented on an AlN substrate with thru-hole. From the measured results, the gain is 24 dB from 13 to 15 GHz and the output power is 33.65 dBm(2.3 W).

• Proceedings of the Korea Inteligent Information System Society Conference
• /
• 2001.01a
• /
• pp.224-229
• /
• 2001

When a semiconductor package is assembled, various materials such as die attach adhesive, lead frame, EMC (Epoxy Molding Compound), and gold wire are used. For better preconditioning performance, the combination between the packaging materials by studying the compatibility of their properties as well as superior packaging material selection is important. But it is not an easy task to find proper packaging material sets, since a variety of factors like package design, substrate design, substrate size, substrate treatment, die size, die thickness, die passivation, and customer requirements should be considered. This research applies case-based reasoning(CBR) technique to solve this problem, utilizing prior cases that have been experienced. Our particular interests lie in building decision support model to aid the selection of proper die attach adhesive. The preliminary results show that this approach is promising.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.05a
• /
• pp.74-78
• /
• 2002

MEMS공정을 이용하여 폴리실리콘의 piezoresistivity를 이용한 스트레인 센서어레이를 제작하였고, 이 센서 어레이를 flexible substrate에 패키징하는 공정을 개발하였다. 실리콘 웨이퍼에 표면 가공(surface micromachining)된 센서는 폴리이미드 코팅, release-etch 방법을 통해 웨이퍼로부터 분리되어 폴리이미드를 기판으로 하는 flexible sensor array module을 완성할 수 있었다. 공정은 희생층과 절연층을 증착하고 폴리실리콘 0.5 $\mu\textrm{m}$을 증착, 도핑 및 패터닝하여 센서 어레이를 구성하였다. 이 센서어레이를 flexible substrate에 패키징 하기 위해서 폴리이미드를 코팅하여 15 $\mu\textrm{m}$의 막을 구성하였고, 100% $O_2$RIE를 이용한 선택적 식각 방법으로 via hole을 구성하였다. 이후 전기도금을 통해 회로를 구성하여 1단계 패키징(die to chip carrier)과 2단계 패키징(chip to substrate)을 웨이퍼 레벨에서 완성하였다. 희생층을 제거함으로서 웨이퍼로부터 센서어레이 모듈을 분리하였다. 제작되어진 센서 모듈은 임의의 곡면에 실장이 가능하도록 충분한 flexibility를 얻을 수 있었다.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.4
• /
• pp.19-23
• /
• 2012

Silicon substrate for light emitting diodes (LEDs) has been the tendency of LED packaging for improving power consumption and light output. In this study, a low cost and high throughput Si through via fabrication has been demonstrated using a wet etching process. Both a wet etching only process and a combination of wet etching and dry etching process were evaluated. The silicon substrate with Si through via fabricated by KOH wet etching showed a good electrical resistance (${\sim}5.5{\Omega}$) of Cu interconnection and a suitable thermal resistance (4 K/W) compared to AlN ceramic substrate.