• 한국전기전자재료학회논문지
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• 제30권5호
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• pp.301-306
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• 2017

Wire electrical discharge machining (WEDM) process was evaluated to slice Silicon (Si) for various applications. Specifically, various Si workpieces with various resistances, such as single and multi crystalline Si bricks and wafers were used. As conventional slicing processes, such as slurry-on or diamond-on wire slicing, are based on mechanical abrasions between Si and abrasive, there is a limitation to decrease the wafer thickness as well as kerf-loss. Especially, when the wafer thickness is less than $150{\mu}m$, wafer breakage increases dramatically during the slicing process. Single crystalline P-type Si bricks and wafers were successively sliced with considerable slicing speed regardless of its growth direction. Also, typical defects, such as microcracks, craters, microholes, and debris, were introduced when Si was sliced by electrical discharge. Also, it was found that defect type is also dependent on resistance of Si. Consequently, this study confirmed the feasibility of slicing single crystalline Si by WEDM.

• 통합자연과학논문집
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• 제3권4호
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• pp.237-240
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• 2010

Recently, number of studies for porous silicon have been investigated by many researchers. Multistructured porous silicon (PSi), distributed Bragg reflector (DBR) PSi, has been a topic of interest, because of its unique optical properties. DBR PSi were prepared by an electrochemical etch of $P^{{+}{+}}$-type silicon wafer of resistivity between 0.1 $m{\Omega}cm$ with square wave current density, resulting two different refractive indices. In this work, We have fabricated a simple and portable organic vapor-sensing device based on DBR porous silicon and investigated the optical characteristics of DBR porous silicon. DBR porous silicon have been characterized by FT-IR, Ocean optics 2000 spectrometer. The device used DBR PSi chip has been demonstrated as an excellent gas sensor, showing a great senstivity to a toxic vapor (TEP, DMMP, DEEP) at room temperature.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.121-124
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• 2004

The research on the porous silicon having low wafer stress during the oxidation process in IPOS(Isolation by Porous Oxidized Silicon) were carried out. Fine pores with less than 100A of diameter were found in the porous silicon which from p-type Si by electrochemical etching. In this study, it is possible to make the porous silicon with 59% of porosity.

• 통합자연과학논문집
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• 제2권4호
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• pp.275-279
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• 2009

Recently, number of studies for porous silicon (PSi) have been investigated by many researchers. Multistructured porous silicon such as a distributed Bragg reflector (DBR) PSi, has been a topic of interest, because of its unique optical properties. DBR PSi were prepared by using an electrochemical etch of $P{^+}{^+}$-type silicon wafer with resistivity between 0.1 and $10m{\Omega}cm$. The electrochemical etch with square wave current density results in two different refractive indices in the porous layer. In this work, DBR porous silicon chips for a simple and portable organic vapor-sensing device have fabricated. The optical characteristics of DBR PSi have been investigated. DBR porous silicon have been characterized by FT-IR and Ocean optics 2000 spectrometer. The device used DBR PSi chip has been demonstrated as an excellent gas sensor, showing a great senstivity to organic vapor at room temperature.

• 한국전기전자재료학회논문지
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• 제36권3호
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• pp.233-240
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• 2023

p-type Tunnel Oxide Passivating Contacts (TOPCon) solar cell is fabricated with a poly-Si/SiO_x structure. It simultaneously achieves surface passivation and enhances the carriers' selective collection, which is a promising technology for conventional solar cells. The quality of passivation is depended on the quality of the tunnel oxide layer at the interface with the c-Si wafer, which is affected by the bond of SiO formed during the subsequent annealing process. The highest cell efficiency reported to date for the laboratory scale has increased to 26.1%, fabricated by the Institute for Solar Energy Research. The cells used a p-type float zone silicon with an interdigitated back contact (IBC) structure that fabricates poly-Si and SiO_x layer achieves the highest implied open-circuit voltage (iV_oc) is 750 mV, and the highest level of edge passivation is 40%. This review presents an overview of p-type TOPCon technologies, including the ultra-thin silicon oxide layer (SiO_x) and poly-silicon layer (poly-Si), as well as the advancement of the SiO_x and poly-Si layers. Subsequently, the limitations of improving efficiency are discussed in detail. Consequently, it is expected to provide a basis for the simplification of industrial mass production.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.332-333
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• 2008

DC magnetron sputtering was used to deposit p-type polycrystalline silicon on n-type Si(100) wafer. The influence of film microstructure properties on deposition parameters (DC power, substrate temperature, pressure) was investigated. The substrate temperature and pressure have the important influence on depositing the poly-Si thin films. Smooth ploy-Si films were obtained in (331) orientation and the average grain sizes are ranged in 25-30nm. The grain sizes of films deposited at low pressure of 10mTorr are a little larger than those deposited at high pressure of 15mTorr.

• 정보저장시스템학회논문집
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• 제2권2호
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• pp.96-99
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• 2006

In this research, a wafer-level transfer method of cantilever away on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• Advances in nano research
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• 제2권1호
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• pp.23-56
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• 2014

The significant growth of the Si photovoltaic industry has been so far limited due to the high cost of the Si photovoltaic system. In this regard, the most expensive factors are the intrinsic cost of silicon material and the Si solar cell fabrication processes. Conventional Si solar cells have p-n junctions inside for an efficient extraction of light-generated charge carriers. However, the p-n junction is normally formed through very expensive processes requiring very high temperature (${\sim}1000^{\circ}C$). Therefore, several systems are currently under study to form heterojunctions at low temperatures. Among them, carbon nanotube (CNT)/Si hybrid solar cells are very promising, with power conversion efficiency up to 15%. In these cells, the p-type Si layer is replaced by a semitransparent CNT film deposited at room temperature on the n-doped Si wafer, thus giving rise to an overall reduction of the total Si thickness and to the fabrication of a device with cheaper methods at low temperatures. In particular, the CNT film coating the Si wafer acts as a conductive electrode for charge carrier collection and establishes a built-in voltage for separating photocarriers. Moreover, due to the CNT film optical semitransparency, most of the incoming light is absorbed in Si; thus the efficiency of the CNT/Si device is in principle comparable to that of a conventional Si one. In this paper an overview of several factors at the basis of this device operation and of the suggested improvements to its architecture is given. In addition, still open physical/technological issues are also addressed.

• Journal of Korean Vacuum Science & Technology
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• 제6권3호
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• pp.120-125
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• 2002

The aim of the present work is to optimized the annealing parameter in both front and back screen printed contacts realization on p-type multicrystalline silicon and with phosphorus diffused. The RTA treatments were carried out at various temperatures from 600 to 850$\^{C}$ and annealing time ranging from 3 min to 5 min in air, O$_2$and N$_2$ ambiance. The contacts parameters are obtained according to Transmission Line Model measurements. A good RTA cycle is obtained with a temperature plateau of 700$\^{C}$-750$\^{C}$ and annealing ambiance of air. Several processing parameters required for good cell efficiency are discussed with an emphasis placed on the critical role of the glass frit in the aluminum paste. A anamolus behaviour of Aluminum n-doping on p-type Si wafer, contact at high temperature have also been studied.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 D
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• pp.1947-1949
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• 1999

Carrier lifetime in silicon power devices caused switching delay and excessive power loss at high frequency switching. We studied transient turn-on/turn-off transient characteristics of electron irradiated and proton irradiated silicon pn junction diodes. Both the electron and proton irradiation of power devices have already become a widely used practice to reduce minority carrier lifetime locally[1]. The sample is n+p junction diode, made by ion implantation on a $20\Omega.cm$ p-type wafer. We investigated turn-on/turn-off transient & breakdown voltage characteristics by digital oscilloscope. Our data show that proton irradiated samples show better performance than electron irradiated samples.